Manufacturing variability analysis in carbon nanotube technology: A comparison with bulk CMOS in 6T SRAM scenario

Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

Volumn , Issue , 2011, Pages 249-254

  García, Carmen ^a   Rubio, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

6T-CELL; 6T-SRAM; BULK CMOS; CARBON NANOTUBE FIELD EFFECT TRANSISTORS; CARBON NANOTUBE TECHNOLOGY; CIRCUIT LEVELS; DEVICE PARAMETERS; LIMITING FACTORS; MANUFACTURING VARIABILITY; METALLIC CARBON NANOTUBES; NANO SCALE; NANOTUBE DIAMETERS; PARAMETER VARIABILITY; POTENTIAL CAPABILITY; STATIC RANDOM ACCESS MEMORY; VARIABILITY MODEL;

CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; MANUFACTURE; SEMICONDUCTING SILICON COMPOUNDS; STATIC RANDOM ACCESS STORAGE;

CARBON NANOTUBES;

EID: 79959977724     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2011.5783088     Document Type: Conference Paper

References (11)

1. (2009) The ITRS website. [Online]. Available: http://www.itrs.net/
2. P. Avouris, "Molecular electronics with carbon nanotubes," Accounts of Chemical Research, vol. 35, pp. 1026-1034, 2002.
3. S. Wind et al., "Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes," Appl. Phys. Lett., vol. 80, pp. 3817-3819, 2002.
4. A. Javey et al., "Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays," Nano Lett., vol. 4, no. 7, pp. 1319-1322, 2004. (Pubitemid 39099196)
5. X. Liu et al., "Detailed analysis of the mean diameter and diameter distribution of single-wall carbon nanotubes from their optical response," Phys. Rev. B, vol. 66, no. 4, 2002.
6. N. Patil, A. Lin, J. Zhang, H. Wong, and S. Mitra, "Digital VLSI logic technology using carbon nanotube FETs: Frequently asked questions," Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE, pp. 304 -309, 2009.
7. N. Patil, J. Deng, S. Mitra, and H.-S. Wong, "Circuit-level performance benchmarking and scalability analysis of carbon nanotube transistor circuits," Nanotechnology, IEEE Transactions on, vol. 8, no. 1, pp. 37- 45, 2009.
8. J. Deng and H.-S. Wong, "A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application part II: Full device model and circuit performance benchmarking," Electron Devices, IEEE Transactions on, vol. 54, no. 12, pp. 3195-3205, 2007. (Pubitemid 350225927)
9. C. T. Sah, "Characteristics of the metal-oxide-semiconductor transistors," IEEE Transactions on Electron Devices, vol. 11, no. 7, pp. 324-345, 1964.
10. (2008) The PTM website. [Online]. Available: http://ptm.asu.edu/
11. M. Meterelliyoz, J. P. Kulkarni, and K. Roy, "Analysis of SRAM and eDRAM cache memories under spatial temperature variations," Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 1, pp. 2-13, 2010.