Multi-level parallelism analysis of face detection on a shared memory multi-core system

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Volumn , Issue , 2011, Pages 328-331

  Chiang, Chih Hsuan ^a   Kao, Chih Heng ^a   Li, Guan Ru ^a   Lai, Bo Cheng Charles ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMIC LEVELS; ANALYSIS RESULTS; COMPREHENSIVE ANALYSIS; COMPUTING SYSTEM; DESIGN EXPERIENCE; EMBEDDED DEVICE; FACE DETECTION ALGORITHM; LIMITING FACTORS; MANY-CORE ARCHITECTURE; MULTI-CORE SYSTEMS; MULTI-LEVEL PARALLELISM; PARALLEL PROCESSING; PARALLELIZATIONS; PERFORMANCE ENHANCEMENTS; PERFORMANCE SCALABILITY; REAL-TIME APPLICATION; SHARED MEMORIES; SMART OBJECTS;

ALGORITHMS; DESIGN; PARALLEL ARCHITECTURES;

PARALLEL PROCESSING SYSTEMS;

EID: 79959503447     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2011.5783540     Document Type: Conference Paper

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