Novel FPGA based haar classifier face detection algorithm acceleration

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2008, Pages 373-378

  Gao, Changjian ^a   Lu, Shih Lien ^b  

^a BROADCOM CORPORATION   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FACE DETECTION ALGORITHMS; FACE DETECTIONS; FALSE POSITIVES; FLEXIBLE; FPGA CHIPS; HI-TECH; HIGH DETECTION RATES; IMPLEMENTING; MICROARCHITECTURE; PARALLEL ARITHMETICS; REAL-TIME PERFORMANCES; VISION ALGORITHMS;

ALGORITHMS; BOOLEAN FUNCTIONS; CLASSIFIERS; LEARNING SYSTEMS; PROGRAM PROCESSORS; SIGNAL DETECTION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 54949097776     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4629966     Document Type: Conference Paper

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