16nm with 193nm immersion lithography and double exposure

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7641, Issue , 2010, Pages

  Axelrad, Valery ^a   Smayling, Michael C ^b  

^a Sequoia Design Systems Inc   (United States)

^b Tela Innovations Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

193NM IMMERSION LITHOGRAPHY; BEFORE AND AFTER; CDS; CO-OPTIMIZATION; DESIGN RULES; DOUBLE EXPOSURE; DOUBLE PATTERNING; ENTRANCE PUPIL; LENS ABERRATION; MANUFACTURABILITY; OPTIMAL SETS; OPTIMIZED CONDITIONS; PATTERN CORRECTION; POLARIZATION EFFECT; PRINTED PATTERNS; PROXIMITY EFFECTS; WORST CASE;

CAPACITANCE; IMAGE QUALITY; LENSES; MACHINE DESIGN; OPTICAL INSTRUMENTS; PHOTOLITHOGRAPHY; VEHICULAR TUNNELS;

OPTIMIZATION;

EID: 77953283591     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.846677     Document Type: Conference Paper

References (5)

1. M. Smayling, V. Axelrad, "Simulation-Based Lithography Optimization for Logic Circuits at 22nm and below," SISPAD, 2009
2. M. Smayling, V. Axelrad, "32nm and below Logic Patterning using Optimized Illumination and Double Patterning," Proc. of SPIE vol. 7274, 2009
3. Y. Borodovsky, "Lithography 2009: Overview of Opportunities," Semicon West, 2009
4. M. C. Smayling, "Gridded Design Rules - 1-D Design Enables Scaling of CMOS Logic," Nanochip Technology Journal, vol. 6(2), (2008).
5. M. Fritze, B. Tyrrell, T. H. Fedynyshyn, M. Rothschild, P. Brooker, "High-Throughput Hybrid Optical Maskless Lithography: All-Optical 32-nm Node Imaging," Proc. of SPIE, vol. 5751, (2005).