Investigation of high-performance sub-50 nm junctionless nanowire transistors

Microelectronics Reliability

Volumn 51, Issue 7, 2011, Pages 1166-1171

  Yan, Ran ^a   Kranti, Abhinav ^a   Ferain, Isabelle ^a   Lee, Chi Woo ^a   Yu, Ran ^a   Dehdashti, Nima ^a   Colinge, Pedram Razavi And Jean Pierre ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DRIVES; DOPING CONCENTRATION; ELECTRICAL CHARACTERISTIC; FIN THICKNESS; FIN WIDTHS; GATE LENGTH; GATE OXIDE THICKNESS; GATE WORK FUNCTION; NANOWIRE TRANSISTORS; PHYSICAL PARAMETERS; SOURCE AND DRAINS; SUB-50 NM; TECHNICAL REQUIREMENT; TECHNOLOGY NODES; VARIABLE PARAMETERS;

ASPECT RATIO; DRAIN CURRENT; FINS (HEAT EXCHANGE); NANOWIRES; THRESHOLD VOLTAGE;

ELECTRIC WIRE;

EID: 79958134148     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2011.02.016     Document Type: Conference Paper

References (6)

1. ITRS roadmap. < http://www.itrs.net >.
2. C.W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, and J.P. Colinge Junctionless multigate field-effect transistor Appl Phys Lett 94 5 2009 053511:1-2
3. C.W. Lee, I. Ferain, A. Afzalian, R. Yan, N. Dehdashti Akhavan, and P. Razavi Performance estimation of junctionless multigate transistors Solid-State Electron 54 2010 97 103
4. J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, and I. Ferain Nanowire transistors without junctions Nat Nanotechnol 5 3 2010 225 229
5. www.silvaco.com.
6. Kranti A, Yan R, Lee C-W, Ferain I, Yu R, Dehdashti Akhavan N, et al. Junctionless nanowire transistor (JNT): properties and design guidelines. In Proceedings of ESSDERC; 2010. p. 357-60.