Three hardware implementations for the binary modular exponentiation: Sequential, parallel and systolic

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn 2003-January, Issue , 2003, Pages 246-253

  Nedjah, N ^a   De Macedo Mourelle, L ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

Computer architecture; Concurrent computing; Delay; Hardware; Iterative algorithms; Parallel architectures; Prototypes; Public key; Public key cryptography; Systems engineering and theory

Indexed keywords

ALGORITHMS; BINS; COMPUTATION THEORY; COMPUTER HARDWARE; CRYPTOGRAPHY; HARDWARE; ITERATIVE METHODS; PARALLEL ARCHITECTURES; PUBLIC KEY CRYPTOGRAPHY;

CONCURRENT COMPUTING; DELAY; ITERATIVE ALGORITHM; PROTOTYPES; PUBLIC KEYS; SYSTEMS ENGINEERING AND THEORIES;

COMPUTER ARCHITECTURE;

EID: 79956140310     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CAHPC.2003.1250344     Document Type: Conference Paper

References (16)

1. R. Rivest, A. Shamir and L. Adleman, A method for obtaining digital signature and public-key cryptosystems, Communications of the ACM, 21:120-126, 1978.
2. P.L. Montgomery, Modular Multiplication without trial division, Mathematics of Computation 44, pp. 519-521, 1985.
3. E. F. Brickell, A survey of hardware implementation of RSA, In G. Brassard, ed., Advances in Crypltology, Proceedings of CRYPTO'98, Lecture Notes in Computer Science 435:368-370, Springer-Verlag, 1989.
4. C. D. Walter, Systolic modular multiplication, IEEE Transactions on Computers, 42(3):376-378, 1993.
5. th. Symposium on Integrated Circuits and Systems Design, Porto Alegre, RS, Brazil, R. Reis and N. Calazans Eds., IEEE Computer Society Press, pp. 3-8, 2002.
6. A. Booth, A signed binary multiplication technique, Quarterly Journal of Mechanics and Applied Mathematics, pp. 236-240, 1951.
7. G. W. Bewick, Fast multiplication algorithms and implementation, Ph. D. Thesis, Department of Electrical Engineering, Stanford University, USA, 1994.
8. C. D. Walter, A verification of Brickell's fast modular multiplication algorithm, International Journal of Computer Mathematics, 33:153:169, 1990.
9. S. E. Eldridge and C. D. Walter, Hardware implementation of Montgomery's Modular Multiplication Algorithm, IEEE Transactions on Computers, 42(6):619-624, 1993.
10. J. Rabaey, Digital integrated circuits: A design perspective, Prentice-Hall, 1995.
11. th. Symposium of Computer Architecture and High Performance Computing, Brasilia, Brazil, A.C. Melo, J. Panetta and M.A. Dantas Eds., pp. 70-75, 2001.
12. N. Nedjah, L. M. Mourelle, Simulation Model for Hardware implementation of modular multiplication, Proceedings of WSES/IEEE International. Conference on Simulation, Knights Island, Malta, September 2001.
13. N. Nedjah, L. M. Mourelle, Reduced hardware architecture for the Montgomery modular multiplication, Proceedings of the third WSEAS/IEEE Symposium Mathematical Methods and Computational Techniques in Electrical Engineering, Athens, Greece, December 2001.
14. N. Nedjah, L. M. Mourelle, Reconfigurable hardware implementation of Montgomery modular multiplication and parallel binary exponentiation, Proceedings of the Euromicro Symposium on Digital System Design, Dortmund, Germany, IEEE Computer Society Press, pp. 226-235, 2002.
15. Z. Navabi, VHDL - Analysis and Modelling of Digital Systems, McGraw Hill, Second Edition, 1998.
16. Xilinx™, Inc. Foundation Series Software, http://www.xilinx.com.