-
1
-
-
58449136605
-
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
-
01
-
H. Zhuang, H. Wang, C. Yap, A. Gutmann, J. Lian, C. Sarma, L. Tsou, A. Gabor, P. Schroeder, S. Halle, K. Herold, H. Haffner, H. Lee, N. Rovedo, C. Chang, H. Ng, D. Shum, R. Wise, M. Hierlemann, and M. Ieong: "Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond", Semiconductor Technology ISTC 2007, Proc. Vol. 2007-01, 154 (2007).
-
(2007)
Semiconductor Technology ISTC 2007, Proc.
, vol.2007
, pp. 154
-
-
Zhuang, H.1
Wang, H.2
Yap, C.3
Gutmann, A.4
Lian, J.5
Sarma, C.6
Tsou, L.7
Gabor, A.8
Schroeder, P.9
Halle, S.10
Herold, K.11
Haffner, H.12
Lee, H.13
Rovedo, N.14
Chang, C.15
Ng, H.16
Shum, D.17
Wise, R.18
Hierlemann, M.19
Ieong, M.20
more..
-
2
-
-
79955840691
-
Sustained scaling for logic applications with DPL?
-
Bolton Landing, NY
-
H. Haffner, S. Postnikov: "Sustained Scaling for Logic Applications with DPL?", Sematech Litho Forum 2008, Bolton Landing, NY (2008).
-
(2008)
Sematech Litho Forum 2008
-
-
Haffner, H.1
Postnikov, S.2
-
3
-
-
77952337060
-
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
-
IEDM
-
F. Arnaud, A. Thean, M. Eller, M. Lipinski, Y.W. Teh, M. Ostermayr, K. Kang, N.S. Kim, K. Ohuchi, J-P. Han, D.R. Nair, J. Lian, S. Uchimura, S. Kohler, S. Miyaki, P. Ferreira, J-H. Park, M. Hamaguchi, K. Miyashita, R. Augur, Q. Zhang, K. Strahrenberg, S. ElGhouli, J. Bonnouvrier, F. Matsuoka, R. Lindsay, J. Sudijono, F.S. Johnson, J.H. Ku, M. Sekine, A. Steegen, R. Sampson: "Competitive and Cost Effective high-k based 28nm CMOS Technology for Low Power Applications", Proc. Electron Devices Meeting, 2009. IEDM 2009.
-
(2009)
Proc. Electron Devices Meeting, 2009
-
-
Arnaud, F.1
Thean, A.2
Eller, M.3
Lipinski, M.4
Teh, Y.W.5
Ostermayr, M.6
Kang, K.7
Kim, N.S.8
Ohuchi, K.9
Han, J.-P.10
Nair, D.R.11
Lian, J.12
Uchimura, S.13
Kohler, S.14
Miyaki, S.15
Ferreira, P.16
Park, J.-H.17
Hamaguchi, M.18
Miyashita, K.19
Augur, R.20
Zhang, Q.21
Strahrenberg, K.22
ElGhouli, S.23
Bonnouvrier, J.24
Matsuoka, F.25
Lindsay, R.26
Sudijono, J.27
Johnson, F.S.28
Ku, J.H.29
Sekine, M.30
Steegen, A.31
Sampson, R.32
more..
-
4
-
-
79955823073
-
Contact patterning strategies for 32- and 28-nm technology
-
B. Morgenfeld, J. An, I. Stobert, M. Aminpur, N. Chen, H. Kanai, A. Thomas, C. Brodsky: "Contact patterning strategies for 32- and 28-nm technology", Proc. SPIE 7973 (2011).
-
(2011)
Proc. SPIE
, vol.7973
-
-
Morgenfeld, B.1
An, J.2
Stobert, I.3
Aminpur, M.4
Chen, N.5
Kanai, H.6
Thomas, A.7
Brodsky, C.8
-
5
-
-
64549128608
-
Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
-
IEDM
-
H. Kawasaki, M. Khater, M. Guillorn, N. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, K. Ishimaru: "Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond", Proc. Electron Devices Meeting, 2008. IEDM 2008.
-
(2008)
Proc. Electron Devices Meeting, 2008
-
-
Kawasaki, H.1
Khater, M.2
Guillorn, M.3
Fuller, N.4
Chang, J.5
Kanakasabapathy, S.6
Chang, L.7
Muralidhar, R.8
Babich, K.9
Yang, Q.10
Ott, J.11
Klaus, D.12
Kratschmer, E.13
Sikorski, E.14
Miller, R.15
Viswanathan, R.16
Zhang, Y.17
Silverman, J.18
Ouyang, Q.19
Yagishita, A.20
Takayanagi, M.21
Haensch, W.22
Ishimaru, K.23
more..
-
6
-
-
33745771310
-
Reducing DfM to practice: The lithography manufacturability assessor
-
L. Liebmann, S. Mansfield, G. Han, J. Culp, J. Hibbeler, and R. Tsai: "Reducing DfM to Practice: the Lithography Manufacturability Assessor", Proc. SPIE 6156, 61560K (2006).
-
(2006)
Proc. SPIE
, vol.6156
-
-
Liebmann, L.1
Mansfield, S.2
Han, G.3
Culp, J.4
Hibbeler, J.5
Tsai, R.6
|