A 2 × 22gb/s SFI5.2 CDR/deserializer in 65nm CMOS technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 10-11

  Nedovic, Nikola ^a   Parikh, Samir ^a   Kristensson, Anders ^a   Tzartzanis, Nestoras ^a   Walker, William ^a   Reddy, Subodh ^a   Tamura, Hirotaka ^b   McLeod, Scott ^a   Yamamoto, Takuji ^b   Doi, Yoshiyasu ^b   Ogawa, Junji ^b   Kibune, Masaya ^b   Shibasaki, Takayuki ^b   Hamada, Takayuki ^b   Tomita, Yasumoto ^b   Ikeuchi, Tadashi ^b,c   Kuwata, Naoki ^b,c  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b FUJITSU LABORATORIES LTD   (Japan)

^c Fujitsu Ltd ^*  (Japan)

Author keywords

CDR; DQPSK; SFI5.2

Indexed keywords

65NM CMOS TECHNOLOGY; CDR; DATA CHANNELS; DESERIALIZERS; DQPSK; LIMITING AMPLIFIERS; SFI5.2; TRIPLE WELL;

CMOS INTEGRATED CIRCUITS; QUADRATURE PHASE SHIFT KEYING;

VLSI CIRCUITS;

EID: 70449376832     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A. Ong, S. Benyamin, V. Condito, et al, "A 40-43Gbp/s Clock and Data Recovery IC with Integrated SFI-5 1:16 Demultiplexor in SiGe Technology," ISSCC Dig. Tech. Papers , pp. 234-235, Feb. 2003.
2. K. Kanda, et al, A 40Gb/s x 1/20Gb/s x2 Serializer IC with SFI5.2 Interface in 65nm CMOS, ISSCC, 2009.
3. Serdes Framer Interface Level 5 Phase 2 Implementation Agreement for 40Bb/s Interface for Physical Layer Devices, Optical Internetworking Forum, Oct. 2, 2006.