An 8MB level-3 cache in 32nm SOI with column-select aliasing

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 258-259

  Weiss, Don ^a   Dreesen, Michael ^a   Ciraula, Michael ^a   Henrion, Carson ^a   Helt, Chris ^a   Freese, Ryan ^a   Miles, Tommy ^a   Karegar, Anita ^a   Schreiber, Russell ^a   Schneller, Bryan ^a   Wuu, John ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

CIRCUIT TECHNIQUES; DATA REQUIREMENTS; HIGH BANDWIDTH; HIGH-K METAL GATES; MULTI-CORE PROCESSOR; MULTI-LEVEL CACHE; SERVER PROCESSORS; TOTAL POWER;

DIGITAL STORAGE;

EID: 79955718518     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746309     Document Type: Conference Paper

References (4)

1. T. Fischer, et al., "Design Solutions for a 32nm SOI 2-core processor module in an 8-core CPU," ISSCC Dig. Tech. Papers, Feb., 2011
2. J. Dorsey, "An Integrated Quad-Core Opteron Processor," ISSCC Dig. Tech. Papers, pp. 102-103, Feb., 2007
3. J. Wuu, et al., "The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium-Family Processor," ISSCC Dig. Tech. Papers, pp. 488-489, Feb., 2005
4. Y. Wang, et al., "A 4.0 GHz 291Mb Voltage-Scalable SRAM Design in 32nm High-K Metal-Gate CMOS with Integrated Power Management," ISSCC Dig. Tech. Papers, pp. 456-457, Feb., 2009.