GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 232-233

  Kurchuk, Mariya ^a   Weltin Wu, Colin ^a   Morche, Dominique ^b   Tsividis, Yannis ^a  

^a Howard Hughes Medical Institute   (United States)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; CONTINUOUS TIME SYSTEMS;

65-NM TECHNOLOGIES; ACTIVITY-DEPENDENT; ANTIALIASING FILTERS; CHANNEL EQUALIZATION; FREQUENCY CAPABILITY; LEVEL-CROSSING SAMPLING; NARROW PULSE WIDTHS; ORDERS OF MAGNITUDE;

ELECTRIC LOSSES;

EID: 79955715776     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746298     Document Type: Conference Paper

References (5)

1. Y. Tsividis, "Continuous-time digital signal processing," Electron. Letters, vol. 39, no. 21, pp. 1551-1552, Oct. 16, 2003.
2. N. Sayiner, H. N. Sorensen, and T. R. Viswanathan, "A level-crossing sampling scheme for A/D conversion", IEEE Trans. Circ. Syst. II, vol. 43, no. 4, pp. 335-339, April 1996.
3. B. Schell and Y. Tsividis, "A continuous-time ADC/DSP/DAC system with no clock and with activity-dependent power dissipation," IEEE J. Solid-State Circuits, vol. 42, pp. 2472-2481, Nov. 2008.
4. th IEEE ISCAS, Paris, France, pp. 3837-3840, May 2010.
5. A. Agrawal et al., "A 320mV to 1.2V on-die fine-grained reconfigurable fabric for DSP/Media accelerators in 32nm CMOS", 2010 IEEE ISSCC Digest, vol. 53, pp. 328-330, Feb. 2010.