Introducing ReConfigME: An operating system for reconfigurable computing

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438, Issue , 2002, Pages 687-697

  Wigley, Grant B ^a   Kearney, David A ^a   Warren, David ^a  

^a UNIVERSITY OF SOUTH AUSTRALIA   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RE-CONFIGURATION; IP CORE; MULTIPLE APPLICATIONS; MULTIPLE USE; OPERATING SYSTEMS; RE-CONFIGURABLE; RECONFIGURABLE COMPUTING;

DYNAMIC MODELS; RECONFIGURABLE HARDWARE; SOFTWARE DESIGN;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79955162076     PISSN: 03029743     EISSN: 16113349     Source Type: Journal    
DOI: 10.1007/3-540-46117-5_71     Document Type: Article

References (13)

1. G. Brebner, "A Virtual Hardware Operating System for the Xilinx XC6200," 6th International Workshop on Field-Programmable Logic and Applications (FPL'96), Darmstadt, Germany, 1996.
2. N. Shirazi, W. Luk, and P. Cheung, "Automating Production of Run-time Reconfigurable Designs," IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'98), Napa Valley, CA, USA, 1998.
3. E. Caspi, A. DeHon, and J. Wawrzynek, "A Streaming Multi-Threaded Model," Third Workshop on Media and Stream Processors, Austin, Texas, 2001.
4. G. Itzstein and D. Kearney, "Applications of Join Java," Seventh Asia-Pacific Computer Systems Architecture Conference (ACSAC02), Melbourne, Australia, 2002.
5. Y. Lamdan and H. Wolfson, "Geometric Hashing: A General and Efficient ModelBased Recognition Scheme," 2nd International Conference on Computer Vision, 1988.
6. D. Warren, "Possible Hardware Implementations of Gemetric Hashing," University of South Australia, Adelaide 2002 2002.
7. S. Guccione, D. Levi, and P. Sundararajan, "JBits: A Java-based Interface for Reconfigurable Computing," 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD).
8. P. Healy and M. Creavin, "An Optimal Algorithm for Rectangle Placement," University of Limerick, Limerick UL-CSIS-97-1, 1997 1997.
9. K. Bazargan, R. Kastner, and M. Sarrafzadeh, "Fast Template Placement for Reconfigurable Computing Systems," in IEEE Design & Test of Computers, vol. 17, 2000, pp. 68-83. (Pubitemid 30574041)
10. S. Gehring and S. Ludwig, "The Trianus System and its Application to Custom Computing," 6th International Workshop on Field-Programmable Logic and Applications (FPL'96), Darmstadt, Germany, 1996.
11. K. Purna and D. Bhatia, "Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers," IEEE Transactions on Computers, vol. 48, pp. 579-590, 1999.
12. A. Raghavan and P. Sutton, "JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs," To appear in Reconfigurable Architecture Workshop (RAW02), 2002.
13. G. Wigley and D. Kearney, "The Management of Applications for Reconfigurable Computing using an Operating System," Seventh Asia-Pacific Computer Systems Architecture Conference, Melbourne, Australia, 2002