메뉴 건너뛰기




Volumn 25, Issue 4, 1990, Pages 942-951

Metastability of CMOS Latch/Flip-Flop

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, CMOS; INTEGRATED CIRCUITS, VLSI; MATHEMATICAL TECHNIQUES--FREQUENCY DOMAIN ANALYSIS; SUBSTRATES--DOPING;

EID: 0025474758     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.58286     Document Type: Article
Times cited : (68)

References (22)
  • 1
    • 0015605213 scopus 로고
    • Anomalous behavior of synchronizer and artiber circuits
    • Apr.
    • T. J. Chaney and C. E. Molnar, “Anomalous behavior of synchronizer and artiber circuits,” IEEE Trans. Computers, vol. C-22, no. 4, pp. 421–422, Apr. 1973.
    • (1973) IEEE Trans. Computers , vol.C-22 , Issue.4 , pp. 421-422
    • Chaney, T.J.1    Molnar, C.E.2
  • 2
    • 0016520116 scopus 로고
    • Theoretical and experimental behavior of synchronizers operating in the metastable region
    • June
    • G. R. Couranz and D. F. Wann, “Theoretical and experimental behavior of synchronizers operating in the metastable region,” IEEE Trans Computers, vol. C-24, no. 6, pp. 604–616, June 1975.
    • (1975) IEEE Trans Computers , vol.C-24 , Issue.6 , pp. 604-616
    • Couranz, G.R.1    Wann, D.F.2
  • 3
    • 0016920527 scopus 로고
    • Anomalous response times of input synchronizers
    • Feb.
    • M. Pěchouček, “Anomalous response times of input synchronizers,” IEEE Trans Computers, vol. C-25, no. 2, pp. 133–139, Feb. 1976.
    • (1976) IEEE Trans Computers , vol.C-25 , Issue.2 , pp. 133-139
    • Pěchouček, M.1
  • 4
    • 0019009609 scopus 로고
    • The behavior of flip-flops used as synchronizers and prediction of their failure rate
    • Apr.
    • H. J. M. Veendrick, “The behavior of flip-flops used as synchronizers and prediction of their failure rate,” IEEE J. Solid-State Circuits, vol. SC-15, no. 2, pp. 169–176, Apr. 1980.
    • (1980) IEEE J. Solid-State Circuits , vol.SC-15 , Issue.2 , pp. 169-176
    • Veendrick, H.J.M.1
  • 5
    • 0020167526 scopus 로고
    • Flip-flop resolving time test circuit
    • Aug.
    • F. Rosenberger and T. J. Chaney, “Flip-flop resolving time test circuit,” IEEE J. Solid-State Circuits, vol. SC-17, no. 4, pp. 731–738, Aug. 1982.
    • (1982) IEEE J. Solid-State Circuits , vol.SC-17 , Issue.4 , pp. 731-738
    • Rosenberger, F.1    Chaney, T.J.2
  • 6
    • 0021405884 scopus 로고
    • Prediction of error probabilities of integrated digital synchronizer
    • Apr.
    • J. H. Hohl, W. R. Larsen, and L. C. Schooley, “Prediction of error probabilities of integrated digital synchronizer,” IEEE J. Solid-State Circuits, vol. SC-19, no. 2, pp. 236–244, Apr. 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SC-19 , Issue.2 , pp. 236-244
    • Hohl, J.H.1    Larsen, W.R.2    Schooley, L.C.3
  • 8
    • 0022102720 scopus 로고
    • Synchronization reliability in CMOS technology
    • Aug.
    • S. T. Flanagan, “Synchronization reliability in CMOS technology,” IEEE J. Solid-State Circuits, vol. SC-20, no. 4, pp. 880–882, Aug. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , Issue.4 , pp. 880-882
    • Flanagan, S.T.1
  • 9
    • 0023293285 scopus 로고
    • Analysis of metastable operation in RS CMOS flip-flops
    • Feb.
    • T. Karprzak and A. Albicki, “Analysis of metastable operation in RS CMOS flip-flops,” IEEE J. Solid-State Circuits, vol. SC-22, no. 1, pp. 57–64, Feb. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , Issue.1 , pp. 57-64
    • Karprzak, T.1    Albicki, A.2
  • 10
    • 0024054668 scopus 로고
    • Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFET’s
    • Aug.
    • T. Sakurai, “Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFET’s,” IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 901–906, Aug. 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.23 , Issue.4 , pp. 901-906
    • Sakurai, T.1
  • 11
    • 0018445468 scopus 로고
    • The anomalous behavior of flip-flops in synchronizer circuits
    • W. Fleischhammer and O. Dörtok, “The anomalous behavior of flip-flops in synchronizer circuits,” IEEE Trans. Computers, vol. C-28, no. 3, pp. 273–276, 1979.
    • (1979) IEEE Trans. Computers , vol.C-28 , Issue.3 , pp. 273-276
    • Fleischhammer, W.1    Dörtok, O.2
  • 13
    • 2342651943 scopus 로고
    • How to avoid synchronization problems
    • Nov.
    • P. A. Stoll, “How to avoid synchronization problems,” VLSI Design, pp. 56–59, Nov. 1982.
    • (1982) VLSI Design , pp. 56-59
    • Stoll, P.A.1
  • 16
    • 0022187644 scopus 로고
    • Effect of study voltage on circuit propagation delay and test applications
    • Nov.
    • K. D. Wagner and E. J. McCluskey, “Effect of study voltage on circuit propagation delay and test applications,” in IEEE IC-CAD Conf. Proc., Nov. 1985, pp. 42–44.
    • (1985) IEEE IC-CAD Conf. Proc. , pp. 42-44
    • Wagner, K.D.1    McCluskey, E.J.2
  • 17
    • 0022102573 scopus 로고
    • Behavior of analog MOS integrated circuits at high temperatures
    • Aug.
    • B. J. Hosticka, K. -G. Dalsaß, D. Krey, and G. Zimmer, “Behavior of analog MOS integrated circuits at high temperatures,” IEEE J. Solid-State Circuits, vol. SC-20, no. 4, pp. 871–874, Aug. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , Issue.4 , pp. 871-874
    • Hosticka, B.J.1    Dalsaß, K.-G.2    Krey, D.3    Zimmer, G.4
  • 18
    • 0024612173 scopus 로고
    • Metastability behavior of CMOS ASIC flip-flops in theory and test
    • Feb.
    • J. U. Horstmann, H. J. W. Eichel, and R. L. Coates, “Metastability behavior of CMOS ASIC flip-flops in theory and test,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 146–157, Feb. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , Issue.1 , pp. 146-157
    • Horstmann, J.U.1    Eichel, H.J.W.2    Coates, R.L.3
  • 19
    • 0024612395 scopus 로고
    • A framework to evaluate technology and device design enhancements for MOS integrated circuits
    • Feb.
    • C. G. Sodini, S. S. Wong, and P.-K. Ko, “A framework to evaluate technology and device design enhancements for MOS integrated circuits,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 118–127, Feb. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , Issue.1 , pp. 118-127
    • Sodini, C.G.1    Wong, S.S.2    Ko, P.-K.3
  • 20
    • 0024056632 scopus 로고
    • Performance limits of mixed analog/digital circuits with scaled MOSFET’s
    • Aug.
    • E. Sano, T. Tsukahara, and A. Iwata, “Performance limits of mixed analog/digital circuits with scaled MOSFET’s,” IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 942–948, Aug. 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.23 , Issue.4 , pp. 942-948
    • Sano, E.1    Tsukahara, T.2    Iwata, A.3
  • 21
    • 0023437909 scopus 로고
    • Static-noise margin analysis of MOS SRAM cell
    • Oct.
    • E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cell,” IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748–754, Oct. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , Issue.5 , pp. 748-754
    • Seevinck, E.1    List, F.J.2    Lohstroh, J.3
  • 22
    • 0023451383 scopus 로고
    • Optimization of LDD MOSFET’s using coupled 2-D simulations
    • Nov.
    • A. Husain, R. Mathur, and S. Wu, “Optimization of LDD MOSFET’s using coupled 2-D simulations,” IEEE Trans Electron Devices, vol. ED-34, no. 11, p. 2386, Nov. 1987.
    • (1987) IEEE Trans Electron Devices , vol.ED-34 , Issue.11 , pp. 2386
    • Husain, A.1    Mathur, R.2    Wu, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.