Debugging unrealizable specifications with model-based diagnosis

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6504 LNCS, Issue , 2011, Pages 29-45

  Könighofer, Robert ^a   Hofferek, Georg ^a   Bloem, Roderick ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR LOCALIZATION; FORMAL SPECIFICATION; MODEL BASED DIAGNOSIS; REACTIVE SYSTEM; REALIZABILITY; UNREALIZABLE CORES;

PROGRAM DIAGNOSTICS; VERIFICATION; SOFTWARE TESTING; SPECIFICATIONS;

SPECIFICATIONS; FORMAL SPECIFICATION;

EID: 79953032413     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-19583-9_8     Document Type: Conference Paper

References (28)

1. Bloem, R., Cimatti, A., Greimel, K., Hofferek, G., Könighofer, R., Roveri, M., Schuppan, V., Seeber, R.: RATSY - A new requirements analysis tool with synthesis. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 425-429. Springer, Heidelberg (2010)
2. Bloem, R., Galler, S., Jobstmann, B., Piterman, N., Pnueli, A., Weiglhofer, M.: Automatic hardware synthesis from specifications: A case study. In: DATE, pp. 1188-1193. ACM, New York (2007) (Pubitemid 47334121)
3. Bloem, R., Galler, S., Jobstmann, B., Piterman, N., Pnueli, A., Weiglhofer, M.: Specify, compile, run: Hardware from PSL. Electronic Notes in Theoretical Computer Science 190(4), 3-16 (2007) (Pubitemid 350017816)
4. Chockler, H., Kupferman, O., Kurshan, R.P., Y. Vardi, M.: A practical approach to coverage in model checking. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, pp. 66-78. Springer, Heidelberg (2001) (Pubitemid 33312905)
5. Cimatti, A., Roveri, M., Schuppan, V., Tchaltsev, A.: Diagnostic information for realizability. In: Logozzo, F., Peled, D.A., Zuck, L.D. (eds.) VMCAI 2008. LNCS, vol. 4905, pp. 52-67. Springer, Heidelberg (2008) (Pubitemid 351358214)
6. Claessen, K.: A coverage analysis for safety property lists. In: FMCAD, pp. 139- 145. IEEE, Los Alamitos (2007)
7. Console, L., Friedrich, G., Theseider Dupré, D.: Model-based diagnosis meets error diagnosis in logic programs. In: IJCAI, pp. 1494-1499. Morgan Kaufmann, San Francisco (1993)
8. Das, S., Banerjee, A., Basu, P., Dasgupta, P., Chakrabarti, P.P., Mohan, C.R., Fix, L.: Formal methods for analyzing the completeness of an assertion suite against a high-level fault model. In: VLSI Design, pp. 201-206. IEEE, Los Alamitos (2005) (Pubitemid 41675272)
9. de Kleer, J., Williams, B.C.: Diagnosing multiple faults. Artificial Intelligence 32(1), 97-130 (1987)
10. Dellacherie, S.: Automatic bus-protocol verification using assertions. In: Global Signal Processing Expo Conference, GSPx (2004)
11. Filiot, E., Jin, N., Raskin, J.-F.: An antichain algorithm for LTL realizability. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 263-277. Springer, Heidelberg (2009)
12. Fisman, D., Kupferman, O., Seinvald, S., Vardi, M.Y.: A framework for inherent vacuity. In: Chockler, H., Hu, A.J. (eds.) HVC 2008. LNCS, vol. 5394, pp. 7-22. Springer, Heidelberg (2009)
13. Hoskote, Y.V., Kam, T., Ho, P.-H., Zhao, X.: Coverage estimation for symbolic model checking. In: DAC, pp. 300-305 (1999)
14. Jobstmann, B., Bloem, R.: Optimizations for LTL synthesis. In: FMCAD, pp. 117- 124. IEEE, Los Alamitos (2006) (Pubitemid 47159932)
15. Katz, S., Grumberg, O., Geist, D.: "Have I written enough properties?" - A method of comparison between specification and implementation. In: Pierre, L., Kropf, T. (eds.) CHARME 1999. LNCS, vol. 1703, pp. 280-297. Springer, Heidelberg (1999)
16. Könighofer, R.: Debugging formal specifications with simplified counterstrategies. Master's thesis, IAIK, Graz University of Technology, Inffeldgasse 16a, A-8010 Graz, Austria (2009)
17. Könighofer, R., Hofferek, G., Bloem, R.: Debugging formal specifications using simple counterstrategies. In: FMCAD, pp. 152-159. IEEE, Los Alamitos (2009)
18. Kozen, D.: Results on the propositional μ-calculus. Theoretical Computer Science 27, 333-354 (1983)
19. Kupferman, O., Vardi, M.Y.: Safraless decision procedures. In: FOCS, pp. 531-542. IEEE, Los Alamitos (2005)
20. Morgenstern, A., Schneider, K.: Exploiting the temporal logic hierarchy and the non-confluence property for efficient LTL synthesis. CoRR abs/1006.1408 (2010)
21. Peischl, B., Wotawa, F.: Automated source-level error localization in hardware designs. IEEE Design and Test of Computers 23, 8-19 (2006) (Pubitemid 43204689)
22. Pill, I., Semprini, S., Cavada, R., Roveri, M., Bloem, R., Cimatti, A.: Formal analysis of hardware requirements. In: DAC, pp. 821-826. ACM, New York (2006) (Pubitemid 47114008)
23. Piterman, N., Pnueli, A., Sa'ar, Y.: Synthesis of reactive(1) designs. In: Emerson, E.A., Namjoshi, K.S. (eds.) VMCAI 2006. LNCS, vol. 3855, pp. 364-380. Springer, Heidelberg (2005) (Pubitemid 43973678)
24. Pnueli, A., Rosner, R.: On the synthesis of a reactive module. In: POPL, pp. 179- 190 (1989)
25. Reiter, R.: A theory of diagnosis from first principles. Artificial Intelligence 32(1), 57-95 (1987)
26. Stumptner, M., Wotawa, F.: Debugging functional programs. In: IJCAI, pp. 1074- 1079. Morgan Kaufmann, San Francisco (1999)
27. Wotawa, F.: Debugging VHDL designs using model-based reasoning. Artificial Intelligence in Engineering 14(4), 331-351 (2000) (Pubitemid 32029225)
28. Zeller, A., Hildebrandt, R.: Simplifying and isolating failure-inducing input. IEEE Transactions on Software Engineering 28(2), 183-200 (2002) (Pubitemid 34198322)