Formal methods for analyzing the completeness of an assertion suite against a high-level fault model

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 201-206

  Das, Sayantan ^a   Banerjee, Ansuman ^a   Basu, Prasenjit ^a   Dasgupta, Pallab ^a   Chakrabarti, P P ^a   Mohan, Chunduri Rama ^b   Fix, Limor ^c  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

^b INTEL CORPORATION   (United States)

^c INTEL CORPORATION   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT MODELS; FORMAL METHODS; FORMAL PROPERTY VERIFICATION (FPV); FORMAL SPECIFICATION;

COMPUTATIONAL COMPLEXITY; MATHEMATICAL MODELS; PROBLEM SOLVING;

INTEGRATED CIRCUIT LAYOUT;

EID: 27944508272     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2005.101     Document Type: Conference Paper

References (8)

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4. Clarke, E.M., Grumberg, O., and Peled, D.A., Model Checking, MIT Press, 2000.
5. Fummi, F., Pravadelli, G., Fedeli, A., Rossi, U., and Toto, F., On the Use of a High-Level Fault Model to Check Properties Incompleteness. In Proc. of MEMOCODE'03, 2003.
6. Hoskote, Y., Kam, T., Ho, PH., and Zao, X., Coverage estimation for symbolic model checking. In Proc. of DAC'99, 300-305, 1999.
7. th ACM POPL 1989, pages 179-190, 1989.
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