FPGA PUF using programmable delay lines

2010 IEEE International Workshop on Information Forensics and Security, WIFS 2010

Volumn , Issue , 2010, Pages

  Majzoobi, Mehrdad ^a   Koushanfar, Farinaz ^a   Devadas, Srinivas ^b  

^a Rice University   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

FPGA; Majority voting; Physical unclonable functions; Programmable delay line; Tuning

Indexed keywords

AVERAGE ERRORS; EFFICIENT IMPLEMENTATION; ENVIRONMENTAL VARIATIONS; EXPERIMENTAL EVALUATION; FINE TUNING; FPGA; HIGH RESOLUTION; INTERNAL STRUCTURE; LOOK UP TABLE; MAJORITY VOTING; METASTABILITIES; PHYSICAL UNCLONABLE FUNCTIONS; PROGRAMMABLE DELAY; PROGRAMMABLE DELAY LINE; PROGRAMMABLE DELAY LINES; SWITCH STRUCTURE; SYSTEMATIC VARIATION; TEMPERATURE VARIATION;

ASYNCHRONOUS SEQUENTIAL LOGIC; ELECTRIC DELAY LINES; TABLE LOOKUP; WAVES;

SECURITY OF DATA;

EID: 79952518421     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WIFS.2010.5711471     Document Type: Conference Paper

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