Advanced technologies for in-line and post-processed TSV integration

ECS Transactions

Volumn 18, Issue 1 PART 2, 2009, Pages 695-700

  Beyne, Eric ^a   Swinnen, Bart ^a   Van Olmen, Jan ^a   Tezcan, Deniz S ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3-D PROCESSING; 3-D SYSTEM INTEGRATION; ADVANCED TECHNOLOGY; APPLICATION DOMAINS; CMOS DEVICES; IN-LINE; INTEGRATION APPROACH; KEY TECHNOLOGIES; POST PROCESS; THROUGH SILICON VIAS; WAFER THINNING;

THREE DIMENSIONAL;

SILICON WAFERS;

EID: 77950656111     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3096523     Document Type: Conference Paper

References (13)

1. E.Beyne, IEEE ISSCC, 15-19 February 2004, San Francisco, pp.138-145 (2004).
2. E.Beyne, IEEE IEDM, 2-5 December 2001, Washington, D.C, S23-p3 (2001).
3. E.Beyne, IEEE IITC, 5-7 June2006, San Francisco, CA, USA, 1-5 (2006).
4. E.Beyne, Semi Technology Symposium, 7 December 2007, Makuhari, Japan, S9P1 (2007).
5. The International Technology Roadmap for Semiconductors, http://www.itrs.net/
6. Jisso: http://jisso.ipc.org/levels-p2.htm
7. D. Sabuncuoglu Tezcan et al, Proc. 57th IEEE ECTC, 29 May - 1 June 2007, Reno, NV, USA (2007).
8. B. Swinnen, et al., IEEE IEDM, 11-13 December 2006, San Francisco, (2006).
9. J. Van Olmen et al., IEEE IEDM, 15-17 December 2008, San Francisco, CA, USA, pp. 603-606 (2006).
10. E. Beyne, 4th Int. Symp. Microelectronic. Packaging, 28 September 2005, Seoul, South Korea (2005).
11. A. Jourdain et al., IEEE IITC, June 2007, San Francisco, CA, USA (2007).
12. K. De Munck et al., IEEE Electron Device Letters, 29, 4, (2008).
13. C. Okoro et al, IEEE IITC, June 2008, San Francisco, CA, USA, pp. 16-18 (2008).