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Volumn , Issue , 2010, Pages 1-4

An implantable neuroprocessor for multichannel compressive neural recording and on-the-fly spike sorting with wireless telemetry

Author keywords

[No Author keywords available]

Indexed keywords

BRAIN MACHINE INTERFACE; CLINICAL APPLICATION; COMMUNICATION CONSTRAINTS; DATA STREAM; IMPLANTABLE DEVICES; IMPLANTABLE MICROELECTRODE ARRAYS; MULTI-CHANNEL; NEURAL DATA; NEURAL INFORMATION; NEURAL RECORDINGS; NEURAL SIGNALS; NEUROPROCESSOR; ON-THE-FLY; SPARSE REPRESENTATION; SPIKE-SORTING; SYSTEM LATENCY; THRESHOLDING; UNIQUE FEATURES; WIRELESS CHANNEL; WIRELESS TELEMETRY;

EID: 79952418050     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BIOCAS.2010.5709556     Document Type: Conference Paper
Times cited : (13)

References (13)
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  • 4
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    • September
    • R. Michael, I. Obeid, S. H. Callender and P. D. Wolf, "A single-chip signal processing and telemetry engine for an implantable 96-channel neural data acquisition system," J. Neural Eng., vol. 4, pp. 309-321, September 2007.
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    • Michael, R.1    Obeid, I.2    Callender, S.H.3    Wolf, P.D.4
  • 5
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    • An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection
    • January
    • Y. Perelman and R. Ginosar, "An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection," IEEE Trans. Biomed. Eng., vol. 54, pp. 130-137, January 2007.
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  • 7
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    • M. S. Chae, Z. Yang, M. R. Yuce, H. Linh, and W. Liu, "A 128-channel 6 mW wireless neural recording IC with spike feature extraction and UWB transmitter," IEEE Trans. Neural Syst. Rehabil. Eng., vol. 17, pp. 312-321, August 2009.
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  • 8
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    • Compressed and distributed sensing of neuronal activity for real time spike train decoding
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  • 9
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    • A scalable wavelet transform VLSI architecture for real-time signal processing in high-density intra-cortical implants
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    • K. G. Oweiss, A. Mason, Y. Suhail, A. M. Kamboh, and K. E. Thomson, "A scalable wavelet transform VLSI architecture for real-time signal processing in high-density intra-cortical implants," IEEE Trans. Circuits Syst. I, vol. 54, pp. 1266-1278, June 2007.
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  • 11
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    • A. M. Kamboh, M. Raetz, K. G. Oweiss, and A. Mason, "Area-power efficient VLSI implementation of multichannel DWT for data compression in implantable neuroprosthetics," IEEE Trans. Biomed. Circuits Syst., vol. 1, pp. 128-135, June 2007.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.