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Volumn , Issue , 2010, Pages 234-237

Intimate mixing of analogue and digital signals in a field-programmable mixed-signal array with lopsided logic

Author keywords

[No Author keywords available]

Indexed keywords

ALL DIGITAL; CLOCK SLEW; CROWBAR CURRENT; D-TYPE FLIP FLOPS; DIGITAL BLOCKS; DIGITAL DOMAIN; DIGITAL FUNCTIONS; DIGITAL SIGNALS; MIXED SIGNAL; NEURAL SIGNAL PROCESSING; PROGRAMMABLE DEVICES;

EID: 79952389857     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BIOCAS.2010.5709614     Document Type: Conference Paper
Times cited : (2)

References (12)
  • 1
    • 0032157579 scopus 로고    scopus 로고
    • A novel switched-capacitor based field-programmable analog array architecture
    • E. Lee and W. Hui, "A novel switched-capacitor based field-programmable analog array architecture," Analog Integrated Circuits and Signal Processing, vol. 17, pp. 35-50, 1998.
    • (1998) Analog Integrated Circuits and Signal Processing , vol.17 , pp. 35-50
    • Lee, E.1    Hui, W.2
  • 3
    • 34547289822 scopus 로고    scopus 로고
    • An aVLSI recurrent network of spiking neurons with reconfigurable and plastic synapses
    • D. Badoni, M. Giulioni, and V. Dante, "An aVLSI recurrent network of spiking neurons with reconfigurable and plastic synapses," in ISCAS, 2006.
    • ISCAS, 2006
    • Badoni, D.1    Giulioni, M.2    Dante, V.3
  • 7
    • 79952388218 scopus 로고    scopus 로고
    • Towards a field programmable analogue array for neural signal processing and neural modelling
    • submitted - note for reviewers, this can be evaluated at
    • S. Bamford and M. Giulioni, "Towards a field programmable analogue array for neural signal processing and neural modelling," in BIOCAS, 2010 - submitted - 〈note for reviewers, this can be evaluated at: http://www.sim.me.uk/neural/2010BIOCAS1.pdf〉.
    • BIOCAS, 2010
    • Bamford, S.1    Giulioni, M.2
  • 9
    • 0030171884 scopus 로고    scopus 로고
    • FPGA and CPLD architectures: A tutorial
    • S. Brown and J. Rose, "FPGA and CPLD architectures: a tutorial," Design & Test of Computers, IEEE, vol. 13S, no. 2, pp. 42-57, 1996.
    • (1996) Design & Test of Computers, IEEE , vol.13 S , Issue.2 , pp. 42-57
    • Brown, S.1    Rose, J.2
  • 11
    • 79952387827 scopus 로고    scopus 로고
    • Flipflop that can tolerate arbitrarily slow clock edges
    • US Patent 7265599
    • R. Pasqualini, "Flipflop that can tolerate arbitrarily slow clock edges," 2007 US Patent 7265599.
    • (2007)
    • Pasqualini, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.