RF CMOS technology scaling in high-k/metal gate era for RF SoC (system-on-chip) applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Jan, C H ^a   Agostinelli, M ^a   Deshpande, H ^a   El Tanani, M A ^a   Hafez, W ^a   Jalan, U ^a   Janbay, L ^a   Kang, M ^a   Lakdawala, H ^a   Lin, J ^a   Lu, Y L ^a   Mudanai, S ^a   Park, J ^a   Rahman, A ^a   Rizk, J ^a   Shin, W K ^a   Soumyanath, K ^a   Tashiro, H ^a   Tsai, C ^a   VanDerVoorn, P ^a   Yeh, J Y ^a   Bai, P ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

32-NM NODE; 90NM NODE; DIGITAL SYSTEM; FLICKER NOISE; GATE TECHNOLOGY; HIGH VOLTAGE TOLERANCE; ORDER OF MAGNITUDE; QUALITY FACTORS; RF CMOS TECHNOLOGY; RF PASSIVES; RF PERFORMANCE; RF-CMOS; SILICON TECHNOLOGIES; STRAINED SILICON; SYSTEM ON CHIPS; TECHNOLOGICAL INNOVATION; TECHNOLOGY SCALING; TRANSISTOR NOISE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; CUTOFF FREQUENCY; ELECTRON DEVICES; NANOTECHNOLOGY; PROGRAMMABLE LOGIC CONTROLLERS; TECHNOLOGY;

INNOVATION;

EID: 79951833151     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703431     Document Type: Conference Paper

References (11)

1. S. Thompson et al., IEDM Tech. Digest, p. 61 (2002)
2. K. Kuhn et al., VLSI Technology Symp., p. 224 (2004)
3. P. Bai et al., IEDM Tech. Digest, p. 657 (2004)
4. C.-H. Jan et al., IEDM Tech. Digest, p. 60 (2005)
5. I. Post et al, IEDM Tech Dig., pp. 1-3 (2006)
6. K. Mistry et al, IEDM Tech Dig., pp. 247-250 (2007)
7. K. Kuhn et al, IEDM Tech Dig., (2007)
8. C.-H. Jan et al, IEDM Tech. Dig., pp. 637-640 (2008)
9. S. Natarajan et al, IEDM Tech. Dig., pp. 941-943 (2008)
10. C.-H. Jan et al, IEDM Tech. Digest, p. 28.1 (2009)
11. P. VanDerVoorn et al, VLSI Tech. Symp., p. 137 (2010)