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Volumn , Issue , 2010, Pages 438-441

Using hard macros to reduce FPGA compilation time

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT BLOCKS; COMPILATION PROCESS; COMPUTATIONAL EFFORT; ERROR PRONES; HARD MACRO; RUNTIMES; TIME-CONSUMING PROCESS;

EID: 79951740392     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2010.90     Document Type: Conference Paper
Times cited : (15)

References (12)
  • 3
    • 84957870821 scopus 로고    scopus 로고
    • VPR: A new packing, placement and routing tool for FPGA research
    • Field-Programmable Logic and Applications
    • V. Betz and J. Rose, "VPR: A New Packing, Placement And Routing Tool For FPGA Research," in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. Springer Verlag London, UK, 1997, pp. 213-222. (Pubitemid 127118755)
    • (1997) LECTURE NOTES IN COMPUTER SCIENCE , Issue.1304 , pp. 213-222
    • Betz, V.1    Rose, J.2
  • 5
    • 0036016182 scopus 로고    scopus 로고
    • Fast placement approaches for FPGAs
    • R. Tessier, "Fast Placement Approaches for FPGAs," ACM Trans. Des. Autom. Electron. Syst., vol. 7, no. 2, pp. 284-305, 2002.
    • (2002) ACM Trans. Des. Autom. Electron. Syst. , vol.7 , Issue.2 , pp. 284-305
    • Tessier, R.1
  • 8
    • 26444588263 scopus 로고    scopus 로고
    • Automated method to generate bitstream intellectual property cores for virtex FPGAs
    • E. L. Horta and J. W. Lockwood, "Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs," in Proc. Field Programmable Logic.2004, 2004.
    • (2004) Proc. Field Programmable Logic. 2004
    • Horta, E.L.1    Lockwood, J.W.2
  • 10
    • 79951763643 scopus 로고    scopus 로고
    • AR #10901 - 6.1i FPGA Editor
    • "AR #10901 - 6.1i FPGA Editor - How do I create a hard macro?" http://www.xilinx.com/support/answers/10901.htm.
    • How do i Create a Hard Macro?
  • 11
    • 79551542957 scopus 로고    scopus 로고
    • Using three-state enable registers in 4000XLA/XV, and spartan-XL FPGAs (XAPP123 v2.0)
    • January
    • "Using Three-State Enable Registers in 4000XLA/XV, and Spartan-XL FPGAs (XAPP123 v2.0)," Xilinx Inc., Tech. Rep., January 2002.
    • (2002) Xilinx Inc., Tech. Rep.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.