Using hard macros to reduce FPGA compilation time

Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010

Volumn , Issue , 2010, Pages 438-441

  Lavin, Christopher ^a   Padilla, Marc ^a   Ghosh, Subhrashankha ^a   Nelson, Brent ^a   Hutchings, Brad ^a   Wirthlin, Michael ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT BLOCKS; COMPILATION PROCESS; COMPUTATIONAL EFFORT; ERROR PRONES; HARD MACRO; RUNTIMES; TIME-CONSUMING PROCESS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79951740392     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2010.90     Document Type: Conference Paper

References (12)

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