-
1
-
-
0033715390
-
New parallelization and convergence results for NC: A negotiation-based FPGA router
-
New York, NY, USA: ACM
-
P. K. Chan and M. D. F. Schlag, "New Parallelization And Convergence Results For NC: A Negotiation-Based FPGA Router," in FPGA 00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays. New York, NY, USA: ACM, 2000, pp. 165-174.
-
(2000)
FPGA 00: Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays
, pp. 165-174
-
-
Chan, P.K.1
Schlag, M.D.F.2
-
3
-
-
84957870821
-
VPR: A new packing, placement and routing tool for FPGA research
-
Field-Programmable Logic and Applications
-
V. Betz and J. Rose, "VPR: A New Packing, Placement And Routing Tool For FPGA Research," in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. Springer Verlag London, UK, 1997, pp. 213-222. (Pubitemid 127118755)
-
(1997)
LECTURE NOTES IN COMPUTER SCIENCE
, Issue.1304
, pp. 213-222
-
-
Betz, V.1
Rose, J.2
-
5
-
-
0036016182
-
Fast placement approaches for FPGAs
-
R. Tessier, "Fast Placement Approaches for FPGAs," ACM Trans. Des. Autom. Electron. Syst., vol. 7, no. 2, pp. 284-305, 2002.
-
(2002)
ACM Trans. Des. Autom. Electron. Syst.
, vol.7
, Issue.2
, pp. 284-305
-
-
Tessier, R.1
-
6
-
-
0032640531
-
Trading quality for compile time: Ultra-fast placement for FPGAs
-
ACM New York, NY, USA
-
Y. Sankar and J. Rose, "Trading Quality For Compile Time: Ultra-Fast Placement For FPGAs," in Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays. ACM New York, NY, USA, 1999, pp. 157-166.
-
(1999)
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays
, pp. 157-166
-
-
Sankar, Y.1
Rose, J.2
-
7
-
-
0031638178
-
A fast routability-driven router for FPGAs
-
New York, NY, USA: ACM
-
J. S. Swartz, V. Betz, and J. Rose, "A Fast Routability-Driven Router For FPGAs," in FPGA 98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays. New York, NY, USA: ACM, 1998, pp. 140-149.
-
(1998)
FPGA 98: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays
, pp. 140-149
-
-
Swartz, J.S.1
Betz, V.2
Rose, J.3
-
8
-
-
26444588263
-
Automated method to generate bitstream intellectual property cores for virtex FPGAs
-
E. L. Horta and J. W. Lockwood, "Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs," in Proc. Field Programmable Logic.2004, 2004.
-
(2004)
Proc. Field Programmable Logic. 2004
-
-
Horta, E.L.1
Lockwood, J.W.2
-
9
-
-
62349103965
-
A fast emulation-based NoC prototyping framework
-
Washington, DC, USA: IEEE Computer Society
-
Y. E. Krasteva, F. Criado, E. d. l. Torre, and T. Riesgo, "A Fast Emulation-Based NoC Prototyping Framework," in RECONFIG 08: Proceedings of the 2008 International Conference on Recon gurable Computing and FPGAs. Washington, DC, USA: IEEE Computer Society, 2008, pp. 211-216.
-
(2008)
RECONFIG 08: Proceedings of the 2008 International Conference on Recon Gurable Computing and FPGAs
, pp. 211-216
-
-
Krasteva, Y.E.1
Criado, F.2
Torre, E.D.L.3
Riesgo, T.4
-
10
-
-
79951763643
-
-
AR #10901 - 6.1i FPGA Editor
-
"AR #10901 - 6.1i FPGA Editor - How do I create a hard macro?" http://www.xilinx.com/support/answers/10901.htm.
-
How do i Create a Hard Macro?
-
-
-
11
-
-
79551542957
-
Using three-state enable registers in 4000XLA/XV, and spartan-XL FPGAs (XAPP123 v2.0)
-
January
-
"Using Three-State Enable Registers in 4000XLA/XV, and Spartan-XL FPGAs (XAPP123 v2.0)," Xilinx Inc., Tech. Rep., January 2002.
-
(2002)
Xilinx Inc., Tech. Rep.
-
-
-
12
-
-
51049103925
-
An XDL-based busmacro generator for customizable communication interfaces for dynamically and partially reconfigurable systems
-
Porto Alegre, Brazil, May
-
C. Claus, B. Zhang, M. Huebner, C. Schmutzler, J. Becker, and W. Stechele, "An XDL-based Busmacro Generator for Customizable Communication Interfaces for Dynamically and Partially Reconfigurable Systems," in Workshop on Recon gurable Computing Education at ISVLSI 2007, Porto Alegre, Brazil, May 2007.
-
(2007)
Workshop on Recon Gurable Computing Education at ISVLSI 2007
-
-
Claus, C.1
Zhang, B.2
Huebner, M.3
Schmutzler, C.4
Becker, J.5
Stechele, W.6
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