Rapid prototyping tools for FPGA designs: RapidSmith

Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

Volumn , Issue , 2010, Pages 353-356

  Lavin, Christopher ^a   Padilla, Marc ^a   Lundrigan, Philip ^a   Nelson, Brent ^a   Hutchings, Brad ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAD SYSTEM; CAD TOOL; COMPILATION PROCESS; FPGA DESIGN; RAPID PROTOTYPING TOOL; SOFTWARE LIBRARIES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RAPID PROTOTYPING;

COMPUTER AIDED DESIGN;

EID: 79551549324     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2010.5681429     Document Type: Conference Paper

References (9)

1. E. L. Horta and J. W. Lockwood, "Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs, " in Proc. Field Programmable Logic.2004, 2004.
2. Y. E. Krasteva, F. Criado, E. d. l. Torre, and T. Riesgo, "A Fast Emulation- Based NoC Prototyping Framework, " in RECONFIG'08: Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs. Washington, DC, USA: IEEE Computer Society, 2008, pp. 211-216.
3. R. Tessier, "Fast Placement Approaches for FPGAs, " ACM Trans. Des. Autom. Electron. Syst., vol. 7, no. 2, pp. 284-305, 2002.
4. C. Lavin, M. Padilla, S. Ghosh, B. Nelson, B. Hutchings, and M. Wirthlin, "Using Hard Macros to Reduce FPGA Compilation Time, " in Proceedings of the 20th International Workshop on Field-Programmable Logic and Applications, 2010, to appear.
5. C. Claus, B. Zhang, M. Huebner, C. Schmutzler, J. Becker, and W. Stechele, "An XDL-based Busmacro Generator for Customizable Communication Interfaces for Dynamically and Partially Reconfigurable Systems, " in Workshop on Reconfigurable Computing Education at ISVLSI 2007, Porto Alegre, Brazil, May 2007.
6. "Using Three-State Enable Registers in 4000XLA/XV, and Spartan-XL FPGAs (XAPP123 v2.0), " Xilinx Inc., Tech. Rep., January 2002.
7. N. Steiner, "A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, " Master's thesis, Virginia Tech, August 2002.
8. K. Kepa, F. Morgan, K. Kósciuszkiewicz, L. Braun, M. Ḧubner, and J. Becker, "FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing, " in ARC'09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications. Berlin, Heidelberg: Springer-Verlag, 2009, pp. 62-73.
9. P. Graham, B. Nelson, and B. Hutchings, "Instrumenting bitstreams for debugging fpga circuits, " Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, vol. 0, pp. 41-50, 2001.