0.5-6 GHz low-voltage low-power mixer using a modified cascode topology in 0.18 μm CMOS technology

IET Microwaves, Antennas and Propagation

Volumn 5, Issue 2, 2011, Pages 167-174

  Liang, K H ^a   Chang, H Y ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; CASCODE TOPOLOGY; CHIP AREAS; CMOS TECHNOLOGY; CONVERSION GAIN; DC POWER; DC SUPPLY VOLTAGE; DOWNCONVERSION MIXER; INJECTION TECHNIQUES; INPUT THIRD-ORDER INTERCEPT POINTS; INTERMEDIATE FREQUENCIES; LOW POWER; LOW-VOLTAGE; RADIO FREQUENCIES; RF BANDWIDTHS; SINGLE-SIDEBAND NOISE; STANDARD CMOS PROCESS; SUPPLY VOLTAGES;

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; DRAIN CURRENT; MIXER CIRCUITS; MIXERS (MACHINERY); MIXING; TOPOLOGY;

DC POWER TRANSMISSION;

EID: 78751514657     PISSN: 17518725     EISSN: 17518733     Source Type: Journal    
DOI: 10.1049/iet-map.2009.0292     Document Type: Article

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