Computation aware scheme for visual signal processing

Journal of Software

Volumn 5, Issue 6, 2010, Pages 573-578

  Paul, Anand ^a   Jiang, Yung Chuan ^a   Wang, Jhing Fa ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

Computation aware system; Dynamic power management; Visual signal processing

Indexed keywords

VIDEO RECORDING; VIDEO SIGNAL PROCESSING;

COMPUTATION POWER; DYNAMIC POWER MANAGEMENT; PROCESSOR RESOURCES; VIDEO CODING ALGORITHM; VIDEO SEQUENCES; VISUAL SIGNAL PROCESSING;

SIGNAL PROCESSING;

EID: 78651527259     PISSN: 1796217X     EISSN: None     Source Type: Journal    
DOI: 10.4304/jsw.5.6.573-578     Document Type: Article

References (15)

1. Joint Video Team of ITU-T and ISODEC JTC I, "Draft ITU-T recommendation and final draft international standard of joint video specification." (ITU-T Kec. H.264 ISO/IEC 14496.10 AVC) JVT of ISO/IEC MPEG and ITU-T VCEG, JVT - GO05 march 2003.
2. T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra "Overview of the H.264/AVC video coding standard", IEEE Transactions on Circuits and Systems for Video Technology, vol.13, no. 7, pp. 560-576, July 2003,
3. P. L. Tsai, S. Y. Huang, C. T. Liu, and J. S. Wang, "Computationaware scheme for software-based block motion estimation," IEEE Trans. Circuits and Syst. Video Technol., vol.13, no. 9, pp. 901-913, Sept. 2003.
4. Yu-Wen Huang and et.al, One-Pass Computation-Aware Motion Estimation with Adaptive Search Strategy. ISCAS 2005 pp. 5469-5472
5. Y. Lu, E. Chung, T. Simuníc, L. Benini and G. De Micheli, "Quantitative Comparison of PM Algorithms", Design, Automation and Test in Europe, pp. 20-26, 2000.
6. L. Benini, G. Paleologo, A. Bogliolo and G. De Micheli, "Policy Optimization for Dynamic Power Management", in IEEE Transactions on Computer-Aided Design, vol. 18, no. 6, pp.813-833, June 1999.
7. E. Chung, L. Benini and G. De Micheli, "Dynamic Power Management for nonstationary service requests", Design, Automation and Test in Europe, pp. 77-81, 1999.
8. W. Stallings, "Computer organization and architecture: designing for performance," Pearson Education, 2003.
9. L. F. Chen, Y. K. Lai, "VLSI architecture of the reconfigurable computing engine for digital signal processing applications," IEEE Circuits and Systems Conference., ISCAS '04. pp. 937-40, May 2004.
10. Vissers, K.A, "Parallel processing architectures for reconfigurable systems," Design, Automation and Test in Europe Conference and Exhibition, 2003 pp. 396 - 397
11. H. Schmit et al, "PipeRench: A virtualized programmable datapath in 0.18 micron technology," IEEE Custom Integrated Circuits Conference., pp. 63-66, May 2002.
12. H. Singh, G. Lu, M. Lee, F. J. Kurdahi, N. Bagherzadeh, E. Filho, R. Maestre, "MorphoSys: Case Study of a Reconfigurable Computing System Targeting Multimedia Applications," Proceedings Design Automation Conference (DAC'00), pp. 573-578, Los Angeles, California, May 2000.
13. R. Maestre, F. J. Kurdahi, M. Fernández, R. Hermida, N. Bagherzadeh, H. Singh, "Kernel Scheduling Techniques for Efficient Solution Space Exploration in Reconfigurable Computing," Special Issue on Modern Methods and Tools in Digital System Design, in the Journal on System Architecture, 47, pp. 277-292, 2001.
14. Q. Qiu and M. Pedram, "Dynamic power management based on continuous-time Markov decision processes", Design Automation Conference, pp. 1999.
15. Comparing System-Level Power Management Policies. Yung-Hsiang Lu, Giovanni De Micheli, Stanford University.