Parallel processing architectures for reconfigurable systems

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 396-397

  Vissers, Kees A ^a,b  

^a Chameleon Systems Inc   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RE-CONFIGURATION; INHERENT PARALLELISM; PARALLEL PROCESSING ARCHITECTURES; PROCESSOR ARCHITECTURES; PROGRAMMING ENVIRONMENT; RECONFIGURABLE COMPUTING ARCHITECTURE; RECONFIGURABLE SYSTEMS; SYSTEM-ON-A-CHIP;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DYNAMIC MODELS; EXHIBITIONS; RECONFIGURABLE ARCHITECTURES; SIGNAL PROCESSING; STRUCTURAL DESIGN;

NETWORK ARCHITECTURE;

EID: 84893721561     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253640     Document Type: Conference Paper

References (0)