Virtual platform architectures for resource metering in datacenters

Performance Evaluation Review

Volumn 37, Issue 2, 2009, Pages 89-90

  Iyer, Ravi ^a   Illikkal, Ramesh ^a   Zhao, Li ^a   Newell, Don ^a   Moses, Jaideep ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Cache memory; CMP; Performance; Quality of service; Resource sharing principles; Service level agreements

Indexed keywords

CMP; DATA CENTERS; DATACENTER; PAY-AS-YOU-GO; PERFORMANCE; RESOURCE SHARING; SERVICE LEVEL AGREEMENTS; UTILITY COMPUTING; VIRTUAL PLATFORM; VIRTUALIZATIONS;

QUALITY CONTROL;

QUALITY OF SERVICE;

EID: 78651443394     PISSN: 01635999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1639562.1639600     Document Type: Conference Paper

References (4)

1. D. Chandra, F. Guo, et al. "Predicting inter-thread cache contention on a chip multiprocessor architecture", 11th International Symposium on High Performance Computer Architecture (HPCA), Feb 2005.
2. R. Iyer, et al, "Datacenter-on-chip Architectures", Intel Technology Journal, 2007
3. Twenty Experts Define Cloud Computing, http://cloudcomputing.syscon.com/ read/612375-p.htm
4. L. Zhao et.al, "CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms", PACT 2007