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Volumn , Issue , 2010, Pages 299-304

Efficient parallelized particle filter design on CUDA

Author keywords

CUDA; GPGPU; Particle filter

Indexed keywords

BEARINGS-ONLY TRACKING; COMPUTING PLATFORM; CUDA; DESIGN TECHNIQUE; EFFICIENT IMPLEMENTATION; FAST PROTOTYPING; GLOBAL OPERATIONS; GPGPU; NONLINEAR APPLICATIONS; PARALLEL SIGNAL PROCESSING; PARTICLE FILTER; PARTICLE FILTER DESIGN; PARTICLE FILTERING; QUANTITATIVE ANALYSIS; RECONFIGURABILITY; RESAMPLING;

EID: 78650335235     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2010.5624805     Document Type: Conference Paper
Times cited : (34)

References (12)
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    • Design methodology for domain specific parameterizable particle filter realizations
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    • S. Hong, J. Lee, A. Athalye, P. M. Djurić, and W.-D. Cho, "Design methodology for domain specific parameterizable particle filter realizations," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 54, no. 9, pp. 1987-2000, Sept. 2007.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.