A 16-bit 100 to 160 MS/s SiGe BiCMOS pipelined ADC with 100 dBFS SFDR

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 12, 2010, Pages 2613-2622

  Payne, Robert ^a   Corsi, Marco ^a   Smith, David ^a   Hsieh, Tien Ling ^a   Kaylor, Scott ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

ADC; analog to digital; complementary bipolar; converter; current mode; linearization; pipeline; SiGe; SOI; trackand hold

Indexed keywords

ADC; ANALOG-TO-DIGITAL; COMPLEMENTARY BIPOLAR; CONVERTER; CURRENT MODE; SIGE; SOI; TRACK-AND-HOLD;

ANALOG TO DIGITAL CONVERSION; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CONVERTERS; ELECTRIC IMPEDANCE; LINEARIZATION; PIPELINES; SIGNAL PROCESSING; SILICON ALLOYS;

SEMICONDUCTING SILICON;

EID: 78650045049     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2074650     Document Type: Conference Paper

References (6)

1. C. Moreland, F. Murden, M. Elliott, J. Young, M. Hensley, and R. Stop, "A 14-bit 100-Msample/s subranging ADC", IEEE J. Solid State Circuits, vol. 35, pp. 1791-1798, Dec. 2000.
2. A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, "A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter", IEEE J. Solid State Circuits, vol. 41, pp. 1846-1855, Aug. 2006.
3. A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, M. Hensley, R. Stop, P. Bhoraskar, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, "A 16 b 250 MS/s IF-sampling pipelined A/D converter with background calibration", in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp. 292-293.
4. S. Devarajan, S. Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath, and P. Wilkins, "A 16 b 125 MS/s 385 mW 78.7 dB SNR CMOS pipeline ADC", in ISSCC Dig. of Technical Papers, Feb. 2009, pp. 86-87.
5. B. El-Kareh, S. Balster, W. Leitz, P. Steinmann, H. Yasuda, M. Corsi, K. Dawoodi, C. Dirnecker, P. Foglietti, A. Haeusler, P. Menz, M. Ramin, T. Scharnagl, M. Schiekofer, M. Schober, U. Schulz, L. Swanson, D. Tatman, M. Waitschull, J. W. Weijtmans, and C. Willis, "A 5 V complementary-SiGe BiCMOS technology for high-speed precision analog circuits", in Proc. Bipolar/BiCMOS Circuits and Technology Meeting, Sep. 2003, pp. 211-214.
6. R. Payne, M. Corsi, D. Smith, D. Hsieh, and S. Kaylor, "A 16 b 100-to-160 MS/s SiGe BiCMOS pipelined ADC with 100 dBFS SFDR", in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp. 294-295.