Single event transient mitigation in cache memory using transient error checking circuits

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Yao, Xiaoyin ^a   Clark, Lawrence T ^a   Patterson, Dan W ^a   Holbert, Keith E ^a  

^a Arizona State University   (United States)

Author keywords

CMOS memory integrated circuits; Heavy ion beams; High speed integrated circuits; Radiation hardening

Indexed keywords

BULK CMOS; CACHE BLOCKS; CMOS MEMORY INTEGRATED CIRCUITS; DATA CORRUPTION; EXPERIMENTAL VALIDATIONS; HIGH-SPEED INTEGRATED CIRCUITS; PERIPHERAL CIRCUITS; PERIPHERY CIRCUITS; RADIATION HARDENED BY DESIGN; SINGLE EVENT TRANSIENTS; TRANSIENT ERRORS;

CACHE MEMORY; DESIGN; ERRORS; HARDENING; HEAVY IONS; INERTIAL CONFINEMENT FUSION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; ION BEAMS; ION ENGINES; RADIATION HARDENING; TRANSIENTS;

CMOS INTEGRATED CIRCUITS;

EID: 78649865546     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617439     Document Type: Conference Paper

References (8)

1. T. Hoang, et al., "A Radiation Hardened 16-Mb SRAM for Space Applications," Proc. IEEE Aerospace Conf., pp. 1-6, Dec. 2006.
2. R. Lacoe, et al., "Application of Hardness-By-Design Methodology to Radiation-Tolerant ASIC Technologies," IEEE Trans. Nuc. Sci., vol. 47, no. 6, Dec. 2000, pp. 2334-2341.
3. R. Baumann, "The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction", Proc. IEDM, pp. 329-332, 2002.
4. K. Mohr and L. Clark, "Delay and Area Efficient First-level Cache Soft Error Detection and Correction," ICCD Proc., pp. 88-92, Oct. 2006.
5. P. McDonald, W. Stapor, A. Campbell, and L. Massengill, "Non-random single event upset trends," IEEE Trans. Nuc. Sci, vol. 36, no. 6, Dec. 1989, pp. 2324-2329.
6. L Jacunski, S. Doyle, D. Jallice, N. Haddan, T. Scott, "SEU immunity: the effects of scaling on the peripheral circuits of SRAMs," IEEE Trans. Nuc. Sci, vol. 41, no. 6, Dec. 1994, pp. 2272-2276.
7. Q. Zhou and K, Mohanram, "Transistor Sizing for Radiation Hardening," Proc. IEEE Int. Reliability Physics Symp., pp. 310-315, 2004.
8. X. Yao, L. Clark, D. Patterson, K. Holbert, "A 90 nm bulk CMOS radiation hardened by design cache memory," IEEE Trans. Nuc. Sci., in press.