Design and implementation of efficient hardware solution based sub-window architecture of Haar classifiers for real-time detection of face biometrics

2010 IEEE International Conference on Mechatronics and Automation, ICMA 2010

Volumn , Issue , 2010, Pages 1563-1568

  Luo, Ren C ^a   Liu, Hsin Hung ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

AdaBoost; Face detection; Field Programmable Gate Array (FPGA); Haar like features; Xilinx system generator

Indexed keywords

ADABOOST; BASIC ELEMENTS; DETECTION PERFORMANCE; FACE DETECTION; FRAME BUFFER; HAAR-LIKE FEATURES; HARDWARE CIRCUITS; HARDWARE SOLUTIONS; INTEGRAL IMAGES; PROPOSED ARCHITECTURES; REAL-TIME DETECTION; REAL-TIME FACE DETECTION; SPEED-UPS; VIDEO DATA; WEAK CLASSIFIERS; XILINX SYSTEM GENERATOR;

ADAPTIVE BOOSTING; BIOMETRICS; CLASSIFIERS; FEATURE EXTRACTION; HARDWARE; LOGIC GATES; MECHATRONICS; VIDEO RECORDING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 78649280651     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMA.2010.5589229     Document Type: Conference Paper

References (14)

1. P. Viola and M. Jones, "Rapid object detection using a boosted cascade of simple features," in Proc. IEEE Conf. Comput. Vis. Pattern Recognit., Dec. 2001, vol. 1, pp. 511-518.
2. L. Shen and L. Bai, "A review on Gabor wavelets for face recognition," Springer London Pattern Analysis & App., vol. 9, no. 2-3, pp. 273-292, Oct. 2006.
3. M. Hiromoto, H. Sugano, and R. Miyamoto, "Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features," IEEE Trans. Circuits and Systems for Video Tech., vol. 19 , no. 1, pp. 41-52, Jan. 2009.
4. M. Hiromoto, K. Nakahara, H. Sugano, Y. Nakamura, and R. Miyamoto, "A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features," IEEE Int. Conf. CVPR, Jun. 2007.
5. C. He, A. Papakonstantinou, and D. Chen, "A Novel SoC Architecture on FPGA for Ultra Fast Face Detection," in Proc. IEEE Int. Conf. Computer Design, Oct. 2009.
6. J. Cho, B. Benson, S. Mirzaei, and R. Kastner, "Parallelized Architecture of Multiple Classifiers for Face Detection," IEEE Int. Conf. ASAP, pp. 75-82, Jul. 2009.
7. S. Jin, D. Kim, T. T. Nguyen, B. Jun, D. Kim, and J. W. Jeon, "An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection Using a Face Certainty Map," IEEE Int. Conf. ASAP, pp. 61-66, Jul. 2009.
8. H.-C. Lai, M. Savvides, and T. Chen, "Proposed FPGA Hardware Architecture for High Frame Rate (≫ 100 fps) Face Detection Using Feature Cascade Classifiers," IEEE Int. Conf. Biometrics: Theory, App., and Systems, pp. 1-6, Sep. 2007.
9. M. Yang, J. Crenshaw, B. Augustine, R. Mareachen, Y. Wu, "Face detection for automatic exposure control in handheld camera," IEEE Int. Conf. ICVS, pp. 17, Jan. 2006.
10. Yu Wei, Xiong Bing, and C. Chareonsak, "FPGA implementation of AdaBoost algorithm for detection of face biometrics," IEEE Int. Workshop Bio. Circuits and Systems, pp. S1/6 - 17-20, Dec. 2004.
11. OpenCV Library Intel Corporation, Santa Clara, CA [Online]. Available: http://sourceforge.net/projects/opencvlibrary/.
12. A Rowe, A. Goode, D. Goel, C. Rosenberg and I. Nourbakhsh, "CMUcam3," Available: http://www.cmucam.org/.
13. Xilinx, "System Generator for DSP - User Guide," Available: http://www.xilinx.com/support/documentation/sw-manuals/xilinx11/sysgen-user.pdf, Dec. 2009.
14. Xilinx, "System Generator for DSP - Reference Guide," Available: http://www.xilinx.com/support/documentation/sw-manuals/xilinx11/ sysgen-ref.pdf, Dec. 2009.