Parallelized architecture of multiple classifiers for face detection

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2009, Pages 75-82

  Junguk, Cho ^a   Benson, Bridget ^a   Mirzaei, Shahnam ^b   Kastner, Ryan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California   (United States)

Author keywords

Face detection; FPGA; Haar classifier; Image processing; Parallel architecture; Real time processing

Indexed keywords

ADABOOST ALGORITHM; CONFIGURABLE; FACE DETECTION; FACE DETECTION SYSTEM; FPGA; HAAR CLASSIFIER; HARDWARE DESIGN; IMAGE SCALING; INTEGRAL IMAGES; MULTIPLE CLASSIFIERS; OBJECT DETECTION METHOD; PARALLEL PROCESSING; PERFORMANCE GAIN; PIPELINED PROCESSING; PROCESSING SPEED; PROPOSED ARCHITECTURES; REAL-TIME PROCESSING; SOFTWARE SOLUTION; VERILOG HDL;

ADAPTIVE BOOSTING; CLASSIFIERS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FACE RECOGNITION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGING SYSTEMS; LEARNING SYSTEMS; PARALLEL ARCHITECTURES; SOFTWARE ARCHITECTURE;

PIPELINE PROCESSING SYSTEMS;

EID: 71049145315     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2009.38     Document Type: Conference Paper

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