Proposed FPGA hardware architecture for high frame rate (>100 fps) face detection using feature cascade classifiers

IEEE Conference on Biometrics: Theory, Applications and Systems, BTAS'07

Volumn , Issue , 2007, Pages

  Lai, Hung Chih ^a   Savvides, Marios ^a   Chen, Tsuhan ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIOMETRICS; CLASSIFICATION (OF INFORMATION); CLASSIFIERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LEAD; LEARNING SYSTEMS; SPEED; WINDOWS;

ADABOOST; ADABOOST BASED FACE DETECTION; AND DETECTION; CASCADE CLASSIFIERS; CURRENT SOFTWARE; DETECTION ACCURACY; DETECTION SPEED; FACE DETECTION; FACE RECOGNITION SYSTEM (FRS); FACE TRACKING; FRAMES PER SECOND (FPS); HARDWARE ARCHITECTURE (GRAPHICS PROCESSORS); HARDWARE ARCHITECTURE DESIGN; HIGH FRAME RATES; HIGH-RESOLUTION (HR) IMAGES; IMAGE SIZES; INTERNATIONAL CONFERENCES; PARALLELIZING; RUNNING SPEED; SINGLE-CLOCK-CYCLE; WEAK CLASSIFIERS; XILINX VIRTEX;

FACE RECOGNITION;

EID: 48649101995     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BTAS.2007.4401930     Document Type: Conference Paper

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