A flexible design flow for software IP binding in FPGA

IEEE Transactions on Industrial Informatics

Volumn 6, Issue 4, 2010, Pages 719-728

  Gora, Michael A ^a   Maiti, Abhranil ^a   Schaumont, Patrick ^a  

^a State University   (United States)

Author keywords

Design flow; field programmable gate arrays (FPGA); firmware; intellectual property; physical unclonable function; secure embedded systems; security; software binding

Indexed keywords

DESIGN FLOWS; PHYSICAL UNCLONABLE FUNCTIONS; SECURE EMBEDDED SYSTEMS; SECURITY; SOFTWARE BINDING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CRYPTOGRAPHY; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; FIRMWARE; INTELLECTUAL PROPERTY; INTERNATIONAL LAW; LOGIC GATES; PROGRAMMABLE LOGIC CONTROLLERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 78149469430     PISSN: 15513203     EISSN: None     Source Type: Journal    
DOI: 10.1109/TII.2010.2068303     Document Type: Article

References (50)

1. G. E. Suh and S. Devadas, "Physical unclonable functions for device authentication and secret key generation," in Proc. 44th ACM/IEEE Design Autom. Conf., DAC'07, Jun. 4-8, 2007, pp. 9-14. [Online]. Available: https://www.trustedcomputinggroup.org/home
2. J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, "Brand and IP protection with physical unclonable functions," in Proc. IEEE Int. Symp. Circuits, Syst., ISCAS'08, May 18-21, 2008, pp. 3186-3189.
3. N. Ferguson and B. Schneier, Practical Cryptography. New York: Wiley.
4. D. Wheeler and R. Needham, TEA Extensions Cambridge Univ., Cambridge, U.K., Tech. Rep., 1997.
5. R. Winternitz, "A secure one-way hash function built from DES," in Proc. IEEE Symp. Informat. Security Privacy, 1984, pp. 88-90. Xilinx Embedded Systems Tool Reference Manual.
6. R. Anderson and M. Kuhn, "Tamper resistance\A cautionary note," in Proc. 2nd USENIX Workshop Electronic Commerce, Nov. 1996, pp. 1-11.
7. S. P. Skorobogatov, "Semi-invasive attacks\A new approach to hardware security analysis," Univ. Cambridge, Cambridge, U.K., Tech. Rep. UCAM-CL-TR-630.
8. C. Bosch, J. Guajardo, A. Sadeghi, J. Shokrollahi, and P. Tuyls, "Efficient helper data key extractor on FPGAs," in Proc. Cryptographic Hardware Embedded Syst., CHES'08, 2008, pp. 181-197
9. Using Bitstream Encryption Xilinx. Inc.
10. J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, "FPGA intrinsic PUFs and their use for IP protection," in Proc. Cryptographic Hardware Embedded Syst., CHES'07, 2007, pp. 63-80.
11. G. E. Suh, C. W. O'Donnell, I. Sachdev, and S. Devadas, "Design and implementation of the AEGIS single-chip secure processor using physical random functions," SIGARCH Comput. Archit. News 33, pp. 25-36, 2005.
12. "Volatile FPGA design security\A survey," Saar Drimer, 2008. [Online]. Available: http://www.cl.cam.ac.uk~sd410/papers/fpga-se-curity.pdf
13. M. J. Atallah, E. D. Bryant, J. T. Korb, and J. R. Rice, "Binding software to specific native hardware in a VM environment: The PUF challenge and opportunity," in Proc. 1st ACM Workshop Virtual Machine Security, Oct 27, 2008, pp. 45-48.
14. C. S. Collberg and C. Thomborson, "Watermarking, tamper-proofing, and obfuscation\Tools for software protection," IEEE Trans. Softw. Eng., vol. 28, no. 8, pp. 735-746, Aug. 2002.
15. B. Horne, L. Matheson, C. Sheehan, and R. E. Tarjan, "Dynamic self-checking techniques for improved tamper resistance," Security and Privacy in Digital Rights Management, vol. 2320, Lecture Notes in Computer Science, pp. 141-159, 2002.
16. H. Chang and M. Atallah, "Protecting software code by guards," Security and Privacy in Digital Rights Management, vol. 2320, Lecture Notes in Computer Science, pp. 160-175, 2002.
17. H. Jin, G. Myles, and J. Lotspiech, "Towards better software tamper resistance," Proc. ISC 2005, vol. 3650, Lecture Notes in Computer Science, pp. 417-430, 2005.
18. X. Zhang, F. He, and W. Zuo, "Hash function based software watermarking," in Proc. Advanced Softw. Eng. Appl., Dec. 13-15, 2008, pp. 95-98.
19. J. Palsberg, S. Krishnaswamy, M. Kwon, D. Ma, Q. Shao, and Y. Zhang, "Experience with software watermarking," in Proc. 16th Annu. Conf. Comput. Security Appl., ACSAC'00, Dec. 2000, pp. 308-316.
20. J. Ge, S. Chaudhuri, and A. Tyagi, "Control flow based obfuscation," in Proc. 5th ACM Workshop on Digital Rights Manage., Nov. 7, 2005, pp. 83-92.
21. W. Michiels and P. Gorissen, "Mechanism for software tamper resistance: An application of white-box cryptography," in Proc. ACM Workshop Digital Rights Manage., Oct. 29, 2007, pp. 82-89.
22. P. van Oorschot, A. Somayaji, and G. Wurster, "Hardware-assisted circumvention of self-hashing software tamper resistance," IEEE Trans. Dependable Secure Comput., vol. 2, no. 2, pp. 82-92, Apr.-Jun. 2005. (Pubitemid 41259858)
23. G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas, "AEGIS: Architecture for tamper-evident and tamper-resistant processing," in Proc. 17th Annu. Int. Conf. Supercomput., Jun. 23-26, 2003, pp. 160-171.
24. J. Stradley and D. Karraker, "The electronic part supply chain and risks of counterfeit parts in defense applications," IEEE Trans. Components and Packaging Technol., vol. 29, no. 3, pp. 703-705, Sep. 2006.
25. The International Anti-Counterfeiting Directory 2002, Counterfeiting Intelligence Bureau, 2005. [Online]. Available: http://www.ic-cwbo.org/ccs/cib- bureau/CIBDir.pdf
26. RF Café\Gray Market (Counterfeit Components), 2006. [Online]. Available: www.rfcafe.com/references/gray-market-links.htm
27. "Managing the risks of counterfeiting in the information technology industry," White Paper, KPMG Electronics, 2005. [Online]. Available: http://www.agmaglobal.org/
28. M. Pecht and S. Tiku, "Bogus: Electronic manufacturing and consumers confront a rising tide of counterfeit electronics," IEEE Spectrum, vol. 43, no. 5, pp. 37-46, May 2006.
29. F. Staake and E. Fleisch, An Introduction to Counterfeit Markets. Berlin, Germany: Springer-Verlag, 2008, pp. 3-21.
30. F. Adelstein, M. Stillerman, and D. Kozen, "Malicious code detection for open firmware," in Proc. 18th Annu. Comput. Security Appl. Conf., 2002, pp. 403-412.
31. C. E. Irvine and K. Levitt, "Trusted hardware: Can it be trustworthy?," in Proc. 44th ACM/IEEE Design Autom. Conf., DAC'07, Jun. 4-8, 2007, pp. 1-4.
32. B. Jun, "Attack of the clones: Building clone-resistant products," in Presentation in Proceedings of RSA Conf., 2006.
33. R. B. Lee, P. Kwan, J. P. McGregor, J. Dwoskin, and Z. Wang, "Architecture for protecting critical secrets in microprocessors," in Proc. 32nd Int. Symp. Comput. Architecture, ISCA'05, Madison, WI, Jun. 4-8, 2005, pp. 2-13.
34. W. A. Arbaugh, D. J. Farber, and J. M. Smith, "A secure and reliable bootstrap architecture," in Proc. IEEE Symp. Security, Privacy, May 4-7, 1997, pp. 65-71.
35. R. Sailer, X. Zhang, T. Jaeger, and L. van Doorn, "Design and implementation of a TCG-based integrity measurement architecture," in Proc. 13th Usenix Security Symp., Aug. 2004, pp. 16-16.
36. D. K. Nilsson and U. E. Larson, "Secure firmware updates over the air in intelligent vehicles," in Proc. IEEE Int. Conf. Commun. Workshops, ICC'08, May 19-23, 2008, pp. 380-384.
37. U. E. Larson and D. K. Nilsson, "Securing vehicles against cyber attacks," in Proc. 4th Annu. Workshop Cyber Security Inform. Intell. Res., CSIIRW'08, 2008, vol. 288.
38. U. E. Larson and D. K. Nilsson, "Securing vehicles against cyber attacks," in Proc. 4th Annu. Workshop Cyber Security Inform. Intell. Res., CSIIRW'08, 2008, vol. 288, pp. 1-3.
39. J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, "Brand and IP protection with physical unclonable functions," in Proc. IEEE Int. Symp. Circuits Syst., ISCAS'08, May 18-21, 2008, pp. 3186-3189.
40. J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, "Physical un-clonable functions and public-key crypto for FPGA IP protection," in Proc. Int. Conf. Field Programmable Logic Appl., FPL'07, Aug. 27-29, 2007, pp. 189-195.
41. H. Krawczyk, M. Bellare, and R. Canetti, "HMAC: Keyed-hashing for message authentication," in Internet RFC 2104. 1997.
42. B. Gassend, D. Clarke, M. van Dijk, and S. Devadas, "Controlled physical random functions," in Proc. 18th Annu. Comput. Security Appl. Conf., 2002, pp. 149-160.
43. A. Maiti and P. Schaumont, "Improving the quality of a physical unclonable function using configurable ring oscillators," in Proc. Int. Conf. Field Programmable Logic Appl., FPL'09, Aug. 2, 2009, pp. 703-707.
44. B. Badrignans, R. Elbaz, and L. Torres, "Secure FPGA configuration architecture preventing system downgrade," in Proc. Int. Conf. Field Programmable Logic App., FPL'08, Sep. 8-10, 2008, pp. 317-322.
45. K. Kepa, F. Morgan, and K. Kosciuszkiewicz, "IP protection in partially reconfigurable FPGAs," in Proc. Int. Conf. Field Programmable Logic Appl., FPL'09, Sep. 2, 2009, pp. 403-409.
46. D.Lie,C.Thekkath,M. Mitchell,P.Lincoln, D.Boneh, J. Mitchell, and Horowitz, "Architectural support for copy and tamper resistant software," in SIGPLAN Not. 35, 2000, pp. 168-177.
47. D. Champagne, R. Elbaz, C. Gebotys, L. Torres, and R. B. Lee, "Forward-secure content distribution to reconfigurable hardware," in Re-configurable Computing and FPGAs, 2008.
48. J. Note and É. Rannaud, "From the bitstream to the netlist," in Proc. 16th Int. ACM/SIGDA Symp. Field Programmable Gate Arrays, Feb. 24-26, 2008, pp. 264-264.
49. P. Athanas, J. Bowen, T. Dunham, C. Patterson, J. Rice, M. Shel-burne, J. Suris, M. Bucciero, and J. Graf, "Wires on demand: Run-time communication synthesis for reconfigurable computing," in Proc. Int. Conf. Field Programmable Logic Appl., FPL'07, Aug. 27-29, 2007, pp. 513-516.
50. R. Torrance, "The state-of-the-art in IC reverse engineering," in Proc. Cryptographic Hardware and Embedded Systems (CHES 2009), vol. 5747, Lecture Notes in Computer Science, pp. 363-381.