IP protection in partially reconfigurable FPGAs

FPL 09: 19th International Conference on Field Programmable Logic and Applications

Volumn , Issue , 2009, Pages 403-409

  Kepa, Krzysztof ^a   Morgan, Fearghal ^a   Kosciuszkiewicz, Krzysztof ^a  

^a NATIONAL UNIVERSITY OF IRELAND   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

BIT STREAM; DESIGN FLOWS; EDA TOOLS; FPGA TECHNOLOGY; IP CORE; IP PROTECTION; PAY-PER-USE; RE-CONFIGURABLE; RECONFIGURABLE CONTROLLERS; RUNTIMES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

INTERNET PROTOCOLS;

EID: 70449926266     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2009.5272250     Document Type: Conference Paper

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