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Volumn , Issue , 2010, Pages 1522-1525

Vector matrix multiplier on field programmable analog array

Author keywords

Analog multiplier; Floating gate; FPAA

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SIGNAL PROCESSING;

EID: 78049414565     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2010.5495508     Document Type: Conference Paper
Times cited : (10)

References (8)
  • 3
    • 33644659163 scopus 로고    scopus 로고
    • Matia: A programmable 80 uw/frame cmos block matrix transform imager architecture
    • A. Bandyopadhyay, Jungwon Lee, R.W. Robucci, and P Hasler, "Matia: a programmable 80 uw/frame cmos block matrix transform imager architecture," IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 663-672, 2006.
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.3 , pp. 663-672
    • Bandyopadhyay, A.1    Lee, J.2    Robucci, R.W.3    Hasler, P.4
  • 4
    • 34247503687 scopus 로고    scopus 로고
    • Sub-microwatt analog vlsi trainable pattern classifier
    • May
    • S. Chakrabartty and G Cauwenberghs, "Sub-microwatt analog vlsi trainable pattern classifier," IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1169-1179, May 2007.
    • (2007) IEEE Journal of Solid-State Circuits , vol.42 , Issue.5 , pp. 1169-1179
    • Chakrabartty, S.1    Cauwenberghs, G.2
  • 7
    • 33747448628 scopus 로고    scopus 로고
    • Placement for large-scale floating-gate field-programable analog arrays
    • Aug.
    • F. Baskaya, S. Reddy, Sung Kyu Lim, and D.V. Anderson, "Placement for large-scale floating-gate field-programable analog arrays," in IEEE Transactions on VLSI Systems, Aug. 2006, vol. 14, pp. 906-910.
    • (2006) IEEE Transactions on VLSI Systems , vol.14 , pp. 906-910
    • Baskaya, F.1    Reddy, S.2    Lim, S.K.3    Anderson, D.V.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.