Performance analysis of the SHA-3 candidates on exotic multi-core architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6225 LNCS, Issue , 2010, Pages 279-293

  Bos, Joppe W ^a   Stefan, Deian ^b  

^a EPFL   (Switzerland)

^b The Cooper Union for the Advancement of Science and Art   (United States)

Author keywords

Cell Broadband Engine; Graphics Processing Unit; Hash function; SHA 3

Indexed keywords

BENCHMARKING; CELLS; COMPUTER GRAPHICS; CYTOLOGY; EMBEDDED SYSTEMS; ENGINES; FUNCTION EVALUATION; GRAPHICS PROCESSING UNIT; HASH FUNCTIONS; IMAGE CODING; PROGRAM PROCESSORS;

ARITHMETIC INSTRUCTIONS; CELL BROADBAND ENGINE; CRYPTOLOGIC RESEARCH; MULTICORE ARCHITECTURES; OPTIMIZATION TECHNIQUES; PERFORMANCE ANALYSIS; SHA-3; SHA-3 CANDIDATES;

COMPUTER ARCHITECTURE;

EID: 78049345430     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-15031-9_19     Document Type: Conference Paper

References (40)

1. American National Standards Institute. ANSI X9.44-2007: Key Establishment Using Integer Factorization Cryptography (2007)
2. Aumasson, J.-P., Henzen, L., Meier, W., Phan, R. C.-W.: SHA-3 proposal BLAKE (2008)
3. Bellare, M., Rogaway, P.: Optimal asymmetric encryption. In: de Santis, A. (ed.) EUROCRYPT 1994. LNCS, vol. 950, pp. 92-111. Springer, Heidelberg (1995)
4. Benadjila, R., Billet, O., Gilbert, H., Macario-Rat, G., Peyrin, T., Robshaw, M., Seurin, Y.: SHA-3 Proposal: ECHO (2009)
5. Benadjila, R., Billet, O., Gueron, S., Robshaw, M. J. B.: The Intel AES instructions set and the SHA-3 candidates. In: Matsui, M. (ed.) ASIACRYPT 2009. LNCS, vol. 5912, pp. 162-178. Springer, Heidelberg (2009)
6. Bernstein, D. J.: CubeHash specification (2. B.1) (2009)
7. Bertoni, G., Daemen, J., Peeters, M., Assche, G. V.: Keccak specifications (2009)
8. Bevand, M.: MD5 Chosen-Prefix Collisions on GPUs. Black Hat, Whitepaper (2009)
9. Biham, E., Dunkelman, O.: The SHAvite-3 Hash Function (2009)
10. Bos, J. W., Casati, N., Osvik, D. A.: Multi-Stream Hashing on the PlayStation 3. In: PARA 2008. LNCS. Springer, Heidelberg (to appear 2008), http://documents.epfl.ch/users/b/bo/bos/public/PARA2008.pdf
11. Bresson, E., Canteaut, A., Chevallier-Mames, B., Clavier, C., Fuhr, T., Gouget, A., Icart, T., Misarsky, J.-F., Naya-Plasencia, M., Paillier, P., Pornin, T., Reinhard, J.-R., Thuillet, C., Videau, M.: The Hash Function Shabal (2008)
12. Canniere, C. D., Sato, H., Watanabe, D.: Hash Function Luffa (2009)
13. Chen, T., Raghavan, R., Dale, J., Iwata, E.: Cell broadband engine architecture and its first implementation: A performance view (November 2005), http://www.ibm.com/developerworks/power/library/pa-cellperf/
14. Daemen, J., Rijmen, V.: The design of Rijndael. Springer, New York (2002)
15. Ferguson, N., Lucks, S., Schneier, B., Whiting, D., Bellare, M., Kohno, T., Callas, J., Walker, J.: The Skein Hash Function Family (2009)
16. Gauravaram, P., Knudsen, L. R., Matusiewicz, K., Mendel, F., Rechberger, C., Schläffer, M., Thomsen, S. S.: Grøstl-a SHA-3 candidate (2008)
17. Gligoroski, D., Klima, V., Knapskog, S. J., El-Hadedy, M., Amundsen, J., Mjo lsnes, S. F.: Cryptographic Hash Function BLUE MIDNIGHT WISH (2009)
18. Halevi, S., Hall, W. E., Jutla, C. S.: The Hash Function Fugue (2009)
19. Harrison, O., Waldron, J.: Practical Symmetric Key Cryptography on Modern Graphics Hardware. In: USENIX Security Symposium, pp. 195-210 (2008)
20. Hofstee, H. P.: Power Efficient Processor Architecture and The Cell Processor. In: HPCA 2005, pp. 258-262. IEEE Computer Society, los Alamitos (2005)
21. IEEE Std 1363-2000. IEEE Standard Specifications for Public-Key Cryptography. IEEE, New York (2000)
22. Krawczyk, H., Bellare, M., Canetti, R.: HMAC: Keyed-Hashing for Message Authentication. RFC 2104, IETF (1997)
23. Küçük, O.: The Hash Function Hamsi (2009)
24. Leurent, G., Bouillaguet, C., Fouque, P.-A.: SIMD Is a Message Digest (2009)
25. Manavski, S. A.: CUDA Compatible GPU as an Efficient Hardware Accelerator for AES Cryptography. In: ICSPC 2007, November 2007, pp. 65-68. IEEE, los Alamitos (2007)
26. Marechal, S.: Advances in password cracking. Journal in Computer Virology 4(1), 73-81 (2008)
27. NIST. FIPS-197: Advanced Encryption Standard (AES) (2001), http://www.csrc.nist.gov/publications/fips/fips197/fips-197.pdf
28. NIST. Secure hash standard. FIPS 180-2 (August 2002), http://www.itl.nist.gov/fipspubs/fip180-2.htm
29. NIST. Announcing request for candidate algorithm nominations for a new cryptographic hash algorithm (SHA-3) family. Technical report, Department of Commerce (November 2007), http://csrc.nist.gov/groups/ST/hash/documents/FR- Notice-Nov07.pdf
30. NVIDIA. NVIDIA Compute. PTX: Parallel Thread Execution (March 2008)
31. NVIDIA. NVIDIA CUDA Programming Guide 2.3 (2009)
32. NVIDIA. NVIDIA's Next Generation CUDA Compute Architecture: Fermi. Whitepaper (September 2009)
33. Osvik, D. A., Bos, J. W., Stefan, D., Canright, D.: Fast software AES encryption. In: beyer, i. (ed.) FSE 2010. LNCS, vol. 6147, pp. 75-93. Springer, Heidelberg (2010)
34. Patterson, D., Hennessy, J.: Computer organization and design: the hardware/software interface. Morgan Kaufmann, San Francisco (2008)
35. Regenscheid, A., Perlner, R., jen Chang, S., Kelsey, J., Nandi, M., Paul., S.: Status report on the first round of the SHA-3 cryptographic hash algorithm competition. Technical Report 7620, NIST (September 2009), http://csrc.nist.gov/groups/ST/hash/sha-3/Round1/documents/sha3NISTIR7620.pdf
36. RSA Laboratories. PKCS #1 v2.1: RSA Cryptography Standard (2002)
37. Stevens, M., Sotirov, A., Appelbaum, J., Lenstra, A., Molnar, D., Osvik, D. A., de Weger, B.: Short chosen-prefix collisions for MD5 and the creation of a rogue CA certificate. In: Halevi, S. (ed.) CRYPTO 2009. LNCS, vol. 5677, pp. 55-69. Springer, Heidelberg (2009)
38. Szerwinski, R., Güneysu, T.: Exploiting the power of GPUs for asymmetric cryptography. In: Oswald, E., Rohatgi, P. (eds.) CHES 2008. LNCS, vol. 5154, pp. 79-99. Springer, Heidelberg (2008)
39. Takahashi, O., Cook, R., Cottier, S., Dhong, S. H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onish, S., Pille, J., Silberman, J.: The circuit design of the synergistic processor element of a Cell processor. In: ICCAD 2005, pp. 111-117. IEEE Computer Society, los Alamitos (2005) (Pubitemid 44815705)
40. Wu, H.: The Hash Function JH (2009)