Fast node merging with don't cares using logic implications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 11, 2010, Pages 1827-1832

  Chen, Yung Chih ^a   Wang, Chun Yao ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Algorithms; circuit optimization; node merging; observability don't cares (ODCs)

Indexed keywords

CIRCUIT OPTIMIZATION; COMPETITIVE CAPABILITIES; EFFICIENCY BENEFITS; LOGIC RESTRUCTURING; NODE MERGING; OPTIMIZATION METHOD; REDUNDANCY REMOVAL; SAT-SOLVING; SATISFIABILITY; STATE-OF-THE-ART METHODS;

MERGERS AND ACQUISITIONS; MERGING; OBSERVABILITY; OPTIMIZATION; SWITCHING CIRCUITS;

LOGIC CIRCUITS;

EID: 77958470588     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2058510     Document Type: Article

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