A 4.84 mm2 847-955 Mb/s 397 mW dual-path fully-overlapped QC-LDPC decoder for the WiMAX system in 0.13 μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 211-212

  Xiang, Bo ^a   Zeng, Xiaoyang ^a  

^a FUDAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK CYCLES; CMOS PROCESSS; DUAL PATH; MEMORY ACCESS; POWER EFFICIENCY; QC-LDPC; SUB-MATRICES; WIMAX SYSTEMS;

CMOS INTEGRATED CIRCUITS; CONVOLUTIONAL CODES; DECODING; ITERATIVE METHODS; WIMAX;

VLSI CIRCUITS;

EID: 77958013195     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560295     Document Type: Conference Paper

References (6)

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3. M. M. Mansour and N. R. Shanbhag, "A 640-Mb/s 2048-bit programmable LDPC decoder chip," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 634-698, Mar. 2006.
4. C.-H. Liu, S.-W. Yen, C.-L. Chen, H.-C. Chang, C.-Y. Lee, Y.-S. Hsu, and S.-J. Jou, "An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications," IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 684-694, Mar. 2008.
5. X.-Y. Shih, C.-Z. Zhan, C.-H. Lin, and A. Y. Wu, "A 19-mode 8.29 mm2 52 mW LDPC Decoder chip for IEEE 802.16e system," in Proc. IEEE Symposium on VLSI Circuits, Jun. 2007, pp. 16-17.
6. T.-C. Kuo and A. N. Willson, "A Flexible Decoder IC for WiMAX QC-LDPC Codes," in Proc. IEEE CICC, Sep. 2008, pp. 527-530.