A 2.8-to-8.5mW GSM/bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CTΔ∑ with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 153-154

  Ke, Yi ^a   Gao, Peng ^a   Craninckx, Jan ^b   Van Der Plas, Geert ^b   Gielen, Georges ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; BIASING CURRENT; COMPONENT PARAMETERS; CONTINUOUS TIME; DIGITAL CMOS; FEED-FORWARD; LOW POWER; OPTIMAL POWER; QUANTIZERS; RE-CONFIGURABLE;

VLSI CIRCUITS;

EID: 77957992117     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560317     Document Type: Conference Paper

References (4)

1. T. Christen, T. Burger, and Q. Huang, "A 0.13um CMOS EDGE/UMTS/WLAN Tri-Mode Δ∑ ADC with - 92dB THD," ISSCC Dig. Tech. Papers, pp. 240-241, Feb. 2007.
2. S. Ouzounov et al., "A 1.2V 121-Mode CT Δ∑ Modulator for Wireless Receivers in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 242-243, Feb. 2007.
3. L. Bos et al., "A Multirate 2.4-to-6.8mW 85-to-66dB DR GSM/Bluetooth/UMTS Cascade DT Δ∑M in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2009.
4. C. Pieter et al. "A 500kHz-10MHz multimode power performance scalable 83-to-67 dB DR CT Δ∑ in 90nm digital CMOS with flexible analog core circuitry," VLSI Circuits, Sym. pp. 70-71, June. 2009.