LEI: A parameterizable VLIW chip-multiprocessor with hardware PThreads support

Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

Volumn , Issue , 2010, Pages 122-126

  Stevens, David ^a   Chouliaras, Vassilios ^b  

^a Department of Electronic and Electrical Engineering ^*  (United Kingdom)

^b LOUGHBOROUGH UNIVERSITY   (United Kingdom)

Author keywords

Chip Multiprocessor (CMP); Configurable; Extensible CPUs; PThreads; VLIW

Indexed keywords

CHIP MULTIPROCESSORS; CONFIGURABLE; EXTENSIBLE CPUS; PTHREADS; VLIW;

PROGRAM PROCESSORS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

MULTIPROCESSING SYSTEMS;

EID: 77957908175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2010.107     Document Type: Conference Paper

References (15)

1. A, Agarwal, M. Levy, 'The KILL Rule for Multicore", Proceedings of the DAC 2007, June 4-8, 2007, San Diego, California, USA.
2. Masakazu Suzuoki, Ken. Kutaragi, Toshiyuki Hiroi, Hidetaka Magoshi, Shin'ichi Okamoto, Masaaki Oka, Akio Ohba, Yasuyuki Yamamoto, Makoto Furuhashi, Masayoshi Tanaka.Teiji Yutaka, Toyoshi Okada, Masato Nagamatsu, Yukihiro Urakawa, Masami Funyu, Atsushi Kunimatsu, Harutaka Goto, Kazuhiro Hashimoto, Nobuhiro Ide, Hiroaki Murakami, Yukio Ohtaguro and Akira Aono, "A. Microprocessor with a 128-Bit CPU, Ten Floating-Point MACs, Four Floating-Point Dividers, and an MPEG-2 Decoder", IEEE Journal of Solid State Circuits, VOL. 34, NO. 11, Nov. 1999
3. B. Ramakrishna Rau and Joseph A, Fisher, "Instruction-Level Parallel Processing: History, Overview, and Perspective", The Journal, of Supercomputing, 7, 9-50 (1993) 9 1993.
4. Vinod Kathail, Shall Aditya, Rob Schreiber, B. Ramakrisha (Bob) Rau, Darren Cronquist, and Mukund Sivaraman, "PICO (Program In, Chip Out): Automatically Designing Custom Computers ", IEEE Computer, vol. 35, no. 9, pp. 39-47, September 2002
5. S. Vassiliadis, G. Gaydadjiev, K. Bertels, "The MOLEN Polymorphic Processor", IEEE TRANSACTIONS ON COMPUTERS, VOL. 53, NO. 11, NOVEMBER 2004, pg. 1363-1375
6. B. Mei, S. Vernalde D. Verkest, H. De Man, R. Lauwereins, "ADRES: an architecture with tightly coupled VLIW processors and coarsegrained reconfigurable matrix ", Proc. Of FPL 2003, pp. 318-327
7. Tay-Jyi Lin, Chun-Nan Liu, Shau-Yin. Tseng, Yuan-Hua Chun-Yeu Wu, "Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform", VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on, 23-25 April 2008, pp. 188-191
8. Pier S. Paolucci, Philippe Kajfasz, Philippe Bonnot, Bernard Candaele, Daniel Maufroid, Elena Pastorelu, Andrea Ricciardi, Yves Fusella, Eugenio Guarino, "mAgic-FPU and MADE:A. customizable VLIW core and the modular VLIW processor architecture description environment", Computer Physics Communications 139 (2001) 132-143
9. Sotirios G. Ziavrasa, Ã, Alexandres V. Gerbessiotisb, Rohan Bafhaa, "Coprocessor design to support MPI primitives in configurable multiprocessors", INTEGRATION, the VLSI journal 40 (2007) 235-252
10. IEEE Standard 1003.1-2001, http://standards.ieee.org/catalog/olis/arch- posix.html. accessed 4 March. 2010
11. Robert p. colwell, robert p. nix, John j. o'donnell, david b. papworth, paul k. rodman., "a vliw architecture for a trace schedulineg compiler", ieee transactions on computers, vol. 37, no. 8, august 1988
12. Rau, Bantwal Ramakrishna; Kathail, Vinod; Aditya, Shall, "MachineDescription Driven Compilers for EPIC Processors", HP Labs Technical Report HPL-98-40
13. V. A. Chouliaras, K. Koutsomyti, T. Jacobs, S. Parr, D. Mulvaney and R. Thomson, "SystemC-defined SIMD instructions for high performance SoC architectures", Proceedings of the 13th IEEE International. Conference on Electronics, Circuits and Systems (ICECS 2006), Nice, France, December 10-13 2006 -
14. J. A. Fischer, P. Faraboschi, "Embedded Computing. A VLIW approach to architectures, compilers and tools", Morgan. Kaufmann publishers, 2005
15. http://www.cs.ucsb.edu/~tvang/class/pth.reads/index-sgi.html, accessed February 2010