A highly efficient modeling style for heterogeneous bus architectures

2003 International Symposium on System-on-Chip, SoC 2003 - Proceedings

Volumn , Issue , 2003, Pages 83-87

  Ariyamparambath, Manoj ^a   Bussaglia, Denis ^a   Reinkemeier, Bernd ^a   Kogel, Tim ^b   Kempf, Torsten ^b  

^a Synopsys GmbH   (Germany)

^b RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTION LEVEL; ARCHITECTURE EXPLORATION; BUS ARCHITECTURE; DESIGN EXPLORATION; DESIGN PERFORMANCE; EXECUTABLE SPECIFICATIONS; FAST SIMULATION; FUNCTIONAL LEVELS; GROUND LAYER; LEVELS OF ABSTRACTION; LOSS OF ACCURACY; ON-CHIP BUS ARCHITECTURE; PERFORMANCE ISSUES; SYSTEM ON CHIP DESIGN; SYSTEMC LANGUAGE;

ABSTRACTING; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUSES; COMPUTER ARCHITECTURE; DESIGN; MICROPROCESSOR CHIPS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 77957799045     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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