Interconnects for novel state variables: Performance modeling and device and circuit implications

IEEE Transactions on Electron Devices

Volumn 57, Issue 10, 2010, Pages 2711-2718

  Rakheja, Shaloo ^a   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Alternate state variable; excitons; interconnects; plasmonics; spintronics

Indexed keywords

CMOS LOGIC; ELECTRON CHARGE; FUNDAMENTAL LAWS; INTERCONNECT TECHNOLOGY; INTERCONNECTS; LOGIC TECHNOLOGY; MOORE'S LAW; PERFORMANCE MODELING; PHYSICAL LOCATIONS; PHYSICAL MODEL; PLASMONICS; POST-CMOS; SPINTRONICS; STATE VARIABLES; TECHNOLOGY ROADMAPS; TRANSPORT MECHANISM; UPPER BOUND;

CMOS INTEGRATED CIRCUITS; EXCITONS; MESFET DEVICES; MODELS; NANOTECHNOLOGY; PLASMONS;

TECHNOLOGY;

EID: 77957013644     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2062186     Document Type: Article

References (29)

1. ITRS 2008 Update on PIDS and Interconnects. [Online]. Available: http://www.itrs.net/Links/2008ITRS/Home2008.htm
2. R. K. Cavin, V. V. Zhirnov, J. A. Hutchby, and G. I. Bourianoff, "Energy barriers, demons, and minimum energy operation of electronic devices," Fluctuation Noise Lett., vol.5, no.4, pp. 29-38, 2005.
3. A. E. Kaloyeros, M. Stan, B. Arkles, R. Geer, E. Eisenbraun, J. Raynolds, A. Gadre, Y. Xue, and J. Ryan, "Conformational molecular switches for post-CMOS nanoelectronics," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.54, no.11, pp. 2345-2352, Nov. 2007.
4. R. K. Cavin, V. V. Zhirnov, D. J. C. Herr, A. Alba, and J. A. Hutchby, "Research directions and challenges in nanoelectronics," J. Nanoparticle Res., vol.8, no.6, pp. 841-858, Dec. 2006.
5. D. D. Awschalom and M. Flatte, "Challenges for semiconductor spintronics," Nat. Phys., vol.3, no.3, pp. 153-159, Mar. 2007.
6. K. Galatsis, A. Khitun, R. Ostroumov, K. L. Wang, W. R. Dichtel, E. Plummer, J. F. Stoddart, J. I. Zink, J. Y. Lee, Y. H. Xie, and K.W. Kim, "Alternate state variables for emerging nanoelectronic devices," IEEE Trans. Nanotechnol., vol.8, no.1, pp. 66-75, Jan. 2009.
7. A. Geim and K. Novoselov, "The rise of graphene," Nat. Mater., vol.6, no.3, pp. 183-191, Mar. 2007.
8. A. Geim and A. H. MacDonald, "Graphene: Exploring carbon flatland," Phys. Today, vol.60, no.8, pp. 35-41, Aug. 2007.
9. J. Su and A. MacDonald, "How to make a graphene bilayer excitons condensate flow," Nat. Phys., vol.4, no.10, pp. 799-802, Oct. 2008.
10. D. Allwood, G. Xiong, C. Faulkner, D. Atkinson, D. Petit, and R. Cowburn, "Magnetic domain-wall logic," Science, vol.309, no.5741, pp. 1688-1692, Sep. 2005.
11. N. Magen, A. Kolondy, U. Weiser, and N. Shamir, "Interconnect-power dissipation in a microprocessor," in Proc. SLIP, 2004, pp. 7-13.
12. P. S. Jose, E. Prada, E. McCann, and H. Schomerus, Pseudospin valve in bilayer graphene: Towards graphene-based pseudospintronics. arXiv: 0901.0889v2.
13. N. Tombros, C. Josza, M. Popinciuc, H. Jonkman, and B. V. Wees, "Electronic spin transport and spin precision in single graphene layers at room temperature," Nature, vol.448, no.7153, pp. 571-574, Aug. 2007.
14. J. Hu, X. Ruan, and Y. Chen, "Thermal conductivity and thermal rectification in graphene nanoribbons: A molecular dynamics study," Nano Lett., vol.9, no.7, pp. 2730-2735, Jul. 2009.
15. R. Dillenschneider and J. H. Han, "Exciton formation in graphene bilayer," Phys. Rev. B, Condens.Matter, vol.78, no.4, p. 045 401, Jul. 2008.
16. T. Ursell, The diffusion equation: A multi-dimensional tutorial, Oct. 2007.
17. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, 1st ed. New York: Springer-Verlag, 1990.
18. R. Skeel and M. Berzins, "A method for the spatial discretization of parabolic equations in one space variable," SIAM J. Sci. Stat. Comput., vol.11, no.1, pp. 1-32, Jan. 1990.
19. L. Wang and B. Li, "Thermal logic gates: Computation with phonons," Phys. Rev. Lett., vol.99, no.17, p. 177 208, Oct. 2007.
20. D. Nika, E. P. Pokatilov, A. Askerov, and A. Balandin, "Phonon thermal conduction in graphene: Role of Umklapp and edge roughness scattering," Phys. Rev. B, Condens. Matter, vol.79, no.15, p. 155 413, Apr. 2009.
21. J. Hone, Carbon Nanotubes: Thermal Properties, 2008, ser. Dekker Encyclopedia of Nanoscience and Nanotechnology.
22. A. Naeemi and J. Meindl, "Design and performance modeling for singlewall carbon nanotubes as local, semi-global, and global interconnects in gigascale integrated systems," IEEE Trans. Electron Devices, vol.54, no.1, pp. 26-37, Jan. 2007.
23. S. Datta, Quantum Transport: Atom to Transistor, 1st ed. Cambridge, U.K.: Cambridge Univ. Press, 2005.
24. A. Khitun, D. E. Nikonov, M. Bao, K. Galatsis, and L. K.Wang, "Feasibility study of logic circuits with a spin wave bus," Nanotechnology, vol.18, no.46, p. 465 202, Nov. 2007.
25. R. de Sousa and J. E. Moore, "Multiferroic materials for spin-based logic devices," J. Nanoelectron. Optoelectron., vol.3, no.1, pp. 77-81, Mar. 2008.
26. A. Khitun, D. Nikonov, M. Bao, K. Galatsis, and K. Wang, "Efficiency of spin-wave bus for information transmission," IEEE Trans. Electron Devices, vol.54, no.12, pp. 3418-3421, Dec. 2007.
27. N. Pyka, L. Pintschovious, and A. Rumiantsev, "High energy spin dynamics of la2cuo4 and la1.9sr0.1cuo4," Z. Phys. B, Condens. Matter, vol.82, pp. 177-181, 1991.
28. L. Pavesi and G. Guillot, Optical Interconnects: The Silicon Approach, 1st ed. New York: Springer-Verlag, 2006.
29. J. Conway, S. Sahni, and T. Szkopek, "Plasmonic interconnects versus conventional interconnects: A comparison of latency, cross-talk and energy costs," Opt. Express, vol.15, no.8, pp. 4474-4484, Apr. 2007.