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ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 189-192

A 25 Gbps inductorless receiver front-end in 65-nm CMOS for serial links

(4) Chujo, Norio a Kamimura, Takehito a Ono, Goichi a Yuki, Fumio a

a HITACHI LTD (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; ACTIVE FEEDBACK; CURRENT TECHNIQUES; DC GAIN; DIFFERENTIAL GAIN; HIGH GAIN; INDUCTORLESS; LIMITING AMPLIFIERS; RECEIVER FRONT-ENDS; REGULATED CASCODE; SERIAL LINK; VARIABLE GAIN AMPLIFIERS;

CMOS INTEGRATED CIRCUITS; FABRICS; VOLTAGE REGULATORS;

AMPLIFIERS (ELECTRONIC);

EID: 77955998159 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2010.5537987 Document Type: Conference Paper

Times cited : (3)

References (6)

1
- 51949104423
- A 21-channel 8Gb/s transceiver macro with 3.6ns latency in 90nm CMOS for 80cm backplane communication
- Jun.
- A. Hayashi, M. Kuwata, K. Suzuki, T. Muto, M. Tsuge, K. Nagashima, D. Hamano, T. Usugi, K. Nakajima, M. Ogihara, N. Mikami, and K. Watanabe, "A 21-channel 8Gb/s transceiver macro with 3.6ns latency in 90nm CMOS for 80cm backplane communication," IEEE Symposium on VLSI Circuits, pp. 202-203, Jun. 2008
- (2008) IEEE Symposium on VLSI Circuits , pp. 202-203
- Hayashi, A.¹ Kuwata, M.² Suzuki, K.³ Muto, T.⁴ Tsuge, M.⁵ Nagashima, K.⁶ Hamano, D.⁷ Usugi, T.⁸ Nakajima, K.⁹ Ogihara, M.¹⁰ Mikami, N.¹¹ Watanabe, K.¹²

2
- 39749093751
- A 24Gb/s software programmable multi-channel transmitter
- Jun.
- A. Amirkhany, A. Abbasfar, J. Savoj, M. Jeeradit, B. Garlepp, V. Stojanovic and M. Horowitz, "A 24Gb/s software programmable multi-channel transmitter," IEEE Symposium on VLSI Circuits, pp. 38-39, Jun. 2007
- (2007) IEEE Symposium on VLSI Circuits , pp. 38-39
- Amirkhany, A.¹ Abbasfar, A.² Savoj, J.³ Jeeradit, M.⁴ Garlepp, B.⁵ Stojanovic, V.⁶ Horowitz, M.⁷

3
- 77955994548
- A 40-Gb/s digitally programmable peaking limiting amplifier with 20-dB differential gain in 90-nm CMOS
- Jun.
- J. R. M. Weiss, M. L. Schmatz and H. Jaeckel, "A 40-Gb/s digitally programmable peaking limiting amplifier with 20-dB differential gain in 90-nm CMOS," Radio Frequency Integrated Circuits Symposium, pp.11-13, Jun. 2006
- (2006) Radio Frequency Integrated Circuits Symposium , pp. 11-13
- Weiss, J.R.M.¹ Schmatz, M.L.² Jaeckel, H.³

4
- 39749188871
- A 35-Gb/s limiting amplifier in 0.13um CMOS Technology
- Jun.
- C. Lee and S. Liu, "A 35-Gb/s limiting amplifier in 0.13um CMOS Technology," IEEE Symposium on VLSI Circuits, pp.122-123, Jun. 2006
- (2006) IEEE Symposium on VLSI Circuits , pp. 122-123
- Lee, C.¹ Liu, S.²

5
- 57849158609
- A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS
- Dec.
- J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally and M. Horowitz, "A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS," IEEE Journal of Solid-state Circuits, vol. 42, pp.2745-2757, Dec. 2007
- (2007) IEEE Journal of Solid-state Circuits , vol.42 , pp. 2745-2757
- Poulton, J.¹ Palmer, R.² Fuller, A.M.³ Greer, T.⁴ Eyles, J.⁵ Dally, W.J.⁶ Horowitz, M.⁷

6
- 0346972289
- 10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-um CMOS Technology
- Dec. 200
- S. Galal and B. Razavi, "10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-um CMOS Technology," IEEE Journal of Solid-state Circuits, vol. 38, pp.2138-2146, Dec. 200.
- IEEE Journal of Solid-state Circuits , vol.38 , pp. 2138-2146
- Galal, S.¹ Razavi, B.²

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