A 35-Gb/s limiting amplifier in 0.13um CMOS technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 122-123

  Lee, Chihun ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; LIGHT AMPLIFIERS; MICROPROCESSOR CHIPS;

LIMITING AMPLIFIER; SINGLE ENDED OUTPUT;

CMOS INTEGRATED CIRCUITS;

EID: 39749188871     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. Y. Baeyens et al, "InP D-HBT ICs for 40-Gb/s and higher bit rate lightwave transceivers," IEEE J. Solid-State Circuits, pp. 1152-1159, Sep. 2002.
4. H. Tran et al, "6-kΩ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range," IEEE J. Solid-State Circuits, pp. 1680-1689, Oct. 2004.
5. S. Galal and B. Razavi, "40-Gb/s amplifier and ESD protection circuit in 0.18um CMOS technology," IEEE J. Solid-State Circuits, pp. 2389-2396, Dec. 2004.
6. B. Y. Banyamin and M. Berwick, "Analysis of the performance of four-cascaded single-stage distributed amplifiers," IEEE Trans. Microwave Theory Tech., pp. 2657-2663, Dec. 2000.
7. C. Lee, Lan-Chou Cho and Shen-Iuan Liu, "A 0.1-25.5-GHz differential cascaded-distributed amplifier in 0.18um CMOS technology," in IEEE Asian Solid-State Circuits Conference Tech. Papers, pp. 129-132, Nov. 2005.