A 21-channel 8Gb/s transceiver macro with 3.6ns latency in 90nm CMOS for 80cm backplane communication

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 202-203

  Hayashi, Atsuhiro ^a   Kuwata, Makoto ^a   Suzuki, Kazuhisa ^a   Muto, Takashi ^a   Tsuge, Masatoshi ^a   Nagashima, Kazuhito ^a   Hamano, Daisuke ^a   Usugi, Tatsunori ^a   Nakajima, Kazunori ^a   Ogihara, Masao ^a   Mikami, Norihisa ^a   Watanabe, Keiki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

JITTER; TRANSCEIVERS; VLSI CIRCUITS;

90-NM CMOS; BACKPLANES; JITTER TOLERANT; LOW-JITTER PLL; PHASE MARGINS; RECEIVER EQUALIZATION; UNCODED;

CMOS INTEGRATED CIRCUITS;

EID: 51949104423     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4586007     Document Type: Conference Paper

References (3)

1. R.Palmer, et al., "A 14mW 6.25Gbps Transceiver in 90nm CMOS for Serial Chip-to-Chip Communication" ISSCC Digest of Technical Papers, pp.440-441, Feb. 2007.
2. Y. Hidaka, et al., "A 4-channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer" ISSCC Digest of Technical Papers, pp.442-443, Feb. 2007.
3. M.Harwood, et al., "A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery" ISSCC Digest of Technical Papers, pp.436-437, Feb. 2007.