An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2001, Pages 638-641

  Olivieri, Mauro ^a   Trijiletti, Alessarzdro ^a  

^a SAPIENZA UNIVERSITY OF ROME   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CELL LIBRARY; CIRCUIT FEATURES; CLOCK CYCLES; CLOCK GENERATOR; EMBEDDED MICROPROCESSORS; FREQUENCY RANGES; MICROPROCESSOR CORE; POWER MANAGEMENTS; WAKE-UP TIME;

MICROPROCESSOR CHIPS; ELECTRIC CLOCKS;

ELECTRIC CLOCKS; DIGITAL LIBRARIES;

EID: 77955990074     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922318     Document Type: Conference Paper

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