0.18 μm CMOS integrated circuit design for impedance-based structural health monitoring

IET Circuits, Devices and Systems

Volumn 4, Issue 3, 2010, Pages 227-238

  Wang, S ^a   Zhao, Z ^a   You, C ^a  

^a North Dakota State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP AREAS; CMOS INTEGRATED CIRCUIT DESIGN; ELECTRICAL IMPEDANCE; ELECTRONIC CIRCUITS; FREQUENCY RANGES; INSPECTION COSTS; MECHANICAL IMPEDANCES; PHYSICAL CHANGES; PIEZOELECTRIC PATCH; POWER CONSUMPTION; STRUCTURAL HEALTH; WIRELESS COMMUNICATION CIRCUITS;

CMOS INTEGRATED CIRCUITS; ELECTRIC IMPEDANCE; ELECTRIC IMPEDANCE MEASUREMENT; HEALTH; INTEGRATED CIRCUIT MANUFACTURE; INTELLIGENT MATERIALS; MONITORING; PIEZOELECTRIC DEVICES; PIEZOELECTRIC MATERIALS; PIEZOELECTRICITY; STRUCTURAL INTEGRITY; WIRELESS TELECOMMUNICATION SYSTEMS;

STRUCTURAL HEALTH MONITORING;

EID: 77955743476     PISSN: 1751858X     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cds.2009.0238     Document Type: Article

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