Field programmable gate array-based Haar classifier for accelerating face detection algorithm

IET Image Processing

Volumn 4, Issue 3, 2010, Pages 184-194

  Gao, C ^a   Lu, S L ^b   Suh, T ^c   Lim, H ^c  

^a BROADCOM CORPORATION   (United States)

^b INTEL CORPORATION   (United States)

^c Korea University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC UNIT; FACE DETECTION; FACE DETECTION ALGORITHM; FALSE POSITIVE; HIGH DETECTION RATE; PIPELINED ARCHITECTURE; REAL TIME PERFORMANCE; RECONFIGURABLE FABRICS; VISION ALGORITHMS;

ALGORITHMS; FABRICS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SIGNAL DETECTION;

CLASSIFIERS;

EID: 77955733883     PISSN: 17519659     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-ipr.2009.0030     Document Type: Article

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