FPGA-based customizable systolic architecture for image processing applications

Proceedings - ReConFig 2005: 2005 International Conference on Reconfigurable Computing and FPGAs

Volumn 2005, Issue , 2005, Pages

  Saldaña, Griselda ^a   Arias Estrada, Miguel ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS;

DATA MEMORY; IMAGE BUFFERS;

COMPUTER ARCHITECTURE;

EID: 33847001638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RECONFIG.2005.20     Document Type: Conference Paper

References (13)

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