Reliability and ultra-low temperature bonding of high density large area arrays with Cu/Sn-Cu interconnects for 3D integration

2010 IEEE International Interconnect Technology Conference, IITC 2010

Volumn , Issue , 2010, Pages

  Reed, Jason D ^a   Lueck, Matthew ^a   Gregory, Chris ^a   Huffman, Charles A ^a   Lannon Jr , John M ^a   Temple, Dorota ^a  

^a RTI INTERNATIONAL   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; BONDING PROCESS; CROSS SECTION; CU-INTERCONNECTS; EDS ANALYSIS; ELECTRICAL YIELD; EUTECTIC BONDING; HIGH DENSITY; INTERMETALLIC COMPOUNDS; LARGE AREA ARRAYS; LIFETIME TESTING; LOW RESISTANCE; LOW THERMAL BUDGET; PRESSURE AND TEMPERATURE; SEM; SHEAR TESTS; ULTRA LOW TEMPERATURES;

EUTECTICS; INTEGRATION; INTERMETALLICS; SHEAR STRENGTH; TIN; TITANIUM COMPOUNDS;

BONDING;

EID: 77955642859     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2010.5510457     Document Type: Conference Paper

References (4)

1. K. Tanida, M. Umemoto, Y Tomita, M. Tago, Y Nemoto, T. Ando, and K. Takahashi, "Ultra-high-density 3D Chip Stacking Technology," Proc. of 2003 ECTC, New Orleans, LA, May 2003, pp. 1084-1089.
2. A. Klumpp, R. Merkel, R. Wieland, and P. Ramm, "Chip-to-Wafer Stacking Technology for 3D System Integration," Proc. of 2003 ECTC, New Orleans, LA, May 2003, pp. 1080-1083.
3. th IITC 2008, pp 46-48.
4. J. D. Reed, M. Lueck, C. Gregory, J. M Lannon, A. Huffman, D. Temple, "High Density Interconnect at 10μm pitch with Mechanically Keyed Cu-Cu/Sn and Cu-Cu Bonding for 3-D Integration", in press.