TLRW: Return of the read-write lock

Annual ACM Symposium on Parallelism in Algorithms and Architectures

Volumn , Issue , 2010, Pages 284-293

  Dice, Dave ^a   Shavit, Nir ^b  

^a Sun Microsystems   (United States)

^b TEL AVIV UNIVERSITY   (Israel)

Author keywords

Multiprocessors; Read write locks; Transactional memory

Indexed keywords

CHIP SYSTEM; COHERENT STATE; EXECUTION PATHS; LOCALITY OF REFERENCE; LOSS OF PERFORMANCE; MULTI CORE; MULTI-CORE SYSTEMS; SINGLE CHIPS; SINGLE-CHIP; SYNCHRONIZATION OPERATION; TRANSACTIONAL MEMORY;

ALGORITHMS; DESIGN; MULTIPROCESSING SYSTEMS; PRIVATIZATION; STORAGE ALLOCATION (COMPUTER);

LOCKS (FASTENERS);

EID: 77954900235     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1810479.1810531     Document Type: Conference Paper

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